47L64 datasheet(13/29 Pages) MICROCHIP

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2019-2020 Microchip Technology Inc.

Preliminary

DS20006168B-page 13

47L64

4.2

DEVICE ADDRESSING

The control byte is the first byte received following the

Start condition from the master device (Figure 4-3).

The control byte begins with a 4-bit op code. The next

two bits are the user-configurable chip select bits, A2

and A1. The next bit is a non-configurable chip select

bit that must always be set to ‘1’. The chip select bits

A2 and A1 in the control byte must match the logic

levels on the corresponding A2 and A1 pins for the

device to respond.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’ a read operation is

selected, and when set to a ‘0’ a write operation is

selected.

The combination of the 4-bit op code and the three

chip select bits is called the slave address. Upon

receiving a valid slave address, the slave device

outputs an Acknowledge signal on the SDA line.

Depending on the state of the R/W bit, the 47L64 will

select a read or a write operation.

FIGURE 4-3:

CONTROL BYTE FORMAT

The 47L64 is divided into two functional units: the

SRAM array and the Control registers.

Section 4.3

“SRAM Array” describes the functionality for the

SRAM array.

The 4-bit op code in the control byte determines which

unit will be accessed during an operation. Table 4-2

shows the standard control bytes used by the 47L64.

TABLE 4-2:

CONTROL BYTES

Note:

When VCAP is below VTRIP, the 47L64

cannot be accessed and will not

acknowledge any commands.

0 A2 A1 1

ACK

R/W

Op Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

Operation

Code

Chip

Select

R/W

Bit

SRAM Read

1010 A2 A1 1

SRAM Write

1010 A2 A1 1

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