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47L64 Datasheet(PDF) 1 Page - Microchip Technology |
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47L64 Datasheet(HTML) 1 Page - Microchip Technology |
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1 / 29 page  2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 1 47L64 Serial SRAM Features • Unlimited Reads/Unlimited Writes: - Standard serial SRAM protocol - Symmetrical timing for reads and writes • SRAM Array: - 8,192 x 8 bits • High-Speed I2C Interface: - Industry standard: 1 MHz, 400 kHz, and 100 kHz - Zero cycle delay writes and reads to SRAM array - Schmitt Trigger inputs for noise suppression • Low-Power CMOS Technology: - Active current: 1 mA (maximum) - Standby current: 200 µA (maximum) Hidden EEPROM Backup Features • Cell-Based Nonvolatile Backup: - Mirrors SRAM array cell-for-cell - Transfers all data to/from SRAM cells in parallel (all cells at same time) • Invisible-to-User Data Transfers: - VCC level monitored inside device - SRAM automatically saved on power disrupt - SRAM automatically restored on VCC return • 100,000 Backups Minimum • 100 Years Retention (at 55°C) Other Features of the 47L64 • Operating Voltage Range: 2.7V to 3.6V • Temperature Ranges: - Industrial (I): -40°C to +85°C • ESD protection: >2,000V Packages • 8-Lead SOIC • 8-Lead TDFN Package Types (not to scale) Pin Descriptions Pin Name Description VCAP External Capacitor A1, A2 Hardware Address Pins VSS Ground SCL Serial Clock Input SDA Serial Data Input/Output WP Write-Protect Input VCC Power Supply 8-Lead SOIC VCAP A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA (Top View) Note 1: Includes Exposed Thermal Pad (EP) TDFN(1) (Top View) A2 A1 VSS WP SCL 1 2 3 4 8 7 6 5 SDA VCC VCAP 64-Kbit I2C EERAM |
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