noise sources such as inductor and SW node, or high frequency clock lines. TI recommends to shield the pair of

remote sensing lines with ground planes above and below.

The recommended GOSNS operating range (refer to AGND pin) is −100 mV to +100 mV. In case of local sense

(no remote sensing), short GOSNS pin to AGND.

7.3.5 Start-up and Shutdown

Start-up

The start-up sequence includes three sequential periods. During the first period, the device does initialization

which includes building up internal LDOs and references, internal memory initialization, pin strap detection, and

so forth. The initialization, which is not gated by EN pin voltage, starts as long as VCC pin voltage is above

the VCC_OK UVLO rising threshold (3.15 V typical). The length of this period is about 300 μs for TPS548C26

device. The pin strap detection result is locked in after the initialization is finished and as long as VCC voltage

stays above VCC_OK falling threshold. Changing the external resistor value does not affect the existing pin strap

detection result unless the IC is power cycled.

After the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second

period, power-on delay. The power-on delay is 0.5 ms to activate the control loop and the driver circuit.

The VOUT soft start is the third period. A soft-start ramp, which is an internal signal, starts right after the power-on

delay. When starting up without pre-bias on the output, the internal reference ramps up from 0 V to 0.8 V, and

the VOUT ramps up from 0 V to the setting value (by FB voltage divider). A proper soft-start time helps to avoid

the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The soft-start time can

be selected among 4 options of 1 ms, 2 ms, 4 ms, and 8 ms by connecting a resistor from pin 29 SS to AGND.

Table 7-1 lists the resistor values and the corresponding soft-start time. TI recommends ±1% tolerance resistors

with a typical temperature coefficient of ±100 ppm/°C.

For the start-up with a pre-biased output the device limits the discharge current from the pre-biased output

voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the

high-side FET. After the increasing reference voltage exceeds the feedback voltage which is divided down from

the pre-biased output voltage, the SW pulses start. This enables a smooth startup with a pre-biased output.

After VOUT reaches the regulation value, a 1-ms PG delay starts. The converter then asserts PG pin when the

1-ms PG delay expires.

Table 7-1. SS Pin Strap for the Soft-start Time, Fault Response, and Internal Compensation

SS Pin to AGND Resistor

(kΩ)

Soft-start time (ms)

Internal Compensation

VOUT OV, UV Fault Response

0

1

Compensation1

Latch-off

1.50

2

2.49

4

3.48

8

4.53

1

Compensation2

5.76

2

7.32

4

8.87

8

10.5

1

Compensation1

Hiccup

12.1

2

14.0

4

16.2

8

18.7

1

Compensation2

21.5

2

24.9

4

28.7

8

TPS548C26

SLVSGM2 – MARCH 2023

www.ti.com

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