The resistor, RILIM, connected from the ILIM pin to AGND sets the overcurrent limit threshold (see the following

table). TI recommends ±1% tolerance resistors with a typical temperature coefficient of ±100 ppm/°C.

Table 7-3. ILIM Pin Strap for Overcurrent Limit Threshold

ILIM Pin to AGND Resistor (kΩ)

OCL Threshold (Valley Current Detection)

7.5

12 A

12.1

19 A

16.2

26 A

21.5

33 A

24.9

39 A

Note

The pin strap detection happens at the first stage of power-up sequence. After the detection finishes,

the detection results are latched in and do not change during the following operation. If a new

selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin

strap detection results.

7.3.10 Negative Overcurrent Limit

The TPS548C26 device is a synchronous buck converter, thus the current can flow from the device to the load

or from the load into the device through SW node. When the current is flowing from the device SW node to the

load the device is said to be sourcing current and the output current declared to be positive. When the current

is flowing into the device SW node from the load, the device is said to be sinking current and the current is

declared to be negative.

The device offers a fixed, cycle-by-cycle negative overcurrent (NOC) limit which is set to −16 A. Similar with the

positive overcurrent limit, the inductor current is monitored during the low-side FET on period. To prevent too

large negative current and a damage of low-side FET, the device turns off the low-side FET after the detected

negative current through the low-side FET exceeds the NOC limit. And then the high-side FET is turned on for

an on-time determined by PVIN, VOUT, and fSW setting. After the high-side FET on-time expires, the low-side

FET turns on again.

The device is unlikely to trigger the −16-A negative current limit during the nominal operation unless too small

inductor value is chosen or the inductor becomes saturated. This NOC operation feature is used to discharge

output capacitors during an overvoltage event.

7.3.11 Zero-Crossing Detection

TPS548C26 device implements an internal circuit for the zero inductor-current detection during skip-mode

operation. The fixed Z-C detection threshold is set to a slightly positive value such as 300 mA to compensate the

delay time of the Z-C detection circuit and avoid too-late detection. Depending on the inductor value, frequency,

VIN and Vout conditions, this can result diode conduction for a short period.

7.3.12 Input Overvoltage Protection

The TPS548C26 device actively monitors the PVIN input voltage. When the PVIN voltage level is above the

input overvoltage threshold, TPS548C26 device stops switching and pulls PG signal low. The PVIN OV rising

threshold is typically 18.6 V while the PVIN OV falling threshold is typically 13.4 V.

After the PVIN overvoltage fault is triggered, the device latches off both the high-side and low-side FETs until the

EN pin is toggled or PVIN is reset.

7.3.13 Output Undervoltage and Overvoltage Protection

The TPS548C26 device monitors the FB node voltage (VFB − VGOSNS) to provide overvoltage (OV) and

undervoltage (UV) protection.

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TPS548C26

SLVSGM2 – MARCH 2023

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