CLC020 datasheet(4/15 Pages) NSC

4 / 15 page

AC Electrical Characteristics (Continued)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

HLD

Hold time

Figure 3

N from PCLK

1.5

GEN

Output inductance

(Note 4)

SDO, SDO

6nH

GEN

Output resistance

(Note 4)

25k

Ω

Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of

these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”

specifies acceptable device operating conditions.

Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS =0V.

Note 3: Typical values are stated for VDD = +5.0V and TA = +25˚C.

Note 4: Specification is guaranteed by design.

Note 5: RL =75Ω, AC-coupled @ 270 Mbps,RREF = 1.69 kΩ 1%, See Test Loads and Figure 2.

Note 6: CLC020 mounted in the SD020EVK board, configured in BIST mode (NTSC color bars) with PCLK = 27MHz derived from Tektronix TG2000 black-burst

reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1kHz filter bandwidth, Hanning window.

Note 7: Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true).

Test Loads

10091703

All resistors in Ohms, 1% tolerance.

FIGURE 1. Test Loads

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