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CLC020 Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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CLC020 Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 15 page ![]() Application Information (Continued) is ground). Configure the SD020EVK to operate in the NTSC colour bars, BIST mode. Configure the VM700T to make the jitter measurement in the jitter FFT mode at the frame rate with 1kHz filter bandwidth and Hanning window. Configure the setup as shown in Figure 9. Switch the test equipment on (from standby mode) and allow all equipment temperatures stabilize per manufacturer’s recommendation. Measure the jitter value after allowing the instrument’s reading to stabilize (about 1 minute). Consult the VM700T Video Measurement Set Option 1S Serial Digital Measurements User Manual (document number 071-0074-00) for details of equipment operation. The VM700T measurement system’s jitter floor specification at 270Mbps is given as 200ps ±20% (100ps ±5% typical) of actual components from 50Hz to 1MHz and 200ps +60%, -30% of actual components from 1MHz to 10MHz. To obtain the actual residual jitter of the CLC020, a root-sum-square adjustment of the jitter reading must be made to compensate for the measurement system’s jitter floor specification. For example, if the jitter reading is 250ps, the CLC020 residual jitter is the square root of (250 2 − 2002) = 150ps. The accuracy limits of the reading as given above apply. 10091710 FIGURE 9. Jitter Test Circuit 10091713 FIGURE 10. ECL-to-TTL/CMOS level converter/amplifer www.national.com 12 |
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