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CLC020 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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CLC020 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 15 page ![]() Device Operation (Continued) TABLE 1. BIST and Test Pattern Generator Control Functions Pin Name Function 3 D0 TPG code input LSB 4 D1 TPG code input 5 D2 TPG code input 6 D3 TPG code input MSB 17 TPG_EN TPG Enable, active high true 26 Test_Out BIST Pass/Fail output. Pass=High (See text for timing requirements) TABLE 2. Component Video Test Pattern Selection Standard Frame Test Pattern D3 D2 D1 D0 NTSC 4x3 Flat-field black 0 0 0 0 NTSC 4x3 PLL pathological 0 0 0 1 NTSC 4x3 EQ pathological 0 0 1 0 NTSC 4x3 Color bars, 75%, 8-bars (modified, see text), BIST 0 0 1 1 PAL 4x3 Flat-field black 0 1 0 0 PAL 4x3 PLL pathological, BIST 0 1 0 1 PAL 4x3 EQ pathological 0 1 1 0 PAL 4x3 Color bars, 75%, 8-bars (modified, see text) 0 1 1 1 NTSC 16x9 Flat-field black 1 0 0 0 NTSC 16x9 PLL pathological 1 0 0 1 NTSC 16x9 EQ pathological 1 0 1 0 NTSC 16x9 Color bars, 75%, 8-bars (modified, see text) 1 0 1 1 PAL 16x9 Flat-field black 1 1 0 0 PAL 16x9 PLL pathological 1 1 0 1 PAL 16x9 EQ pathological 1 1 1 0 PAL 16x9 Color bars, 75%, 8-bars (modified, see text) 1 1 1 1 Note: D9 through D4 = 0 (binary) 10091707 FIGURE 6. Test Pattern Generator Control Sequence www.national.com 8 |
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