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HC705RC16GRS/D Datasheet(PDF) 111 Page - NXP Semiconductors |
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HC705RC16GRS/D Datasheet(HTML) 111 Page - NXP Semiconductors |
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111 / 120 page ![]() Electrical Specifications DC Electrical Characteristics (3.3 Vdc) MC68HC705RC16 — Rev. 3.0 General Release Specification Electrical Specifications 12.7 DC Electrical Characteristics (3.3 Vdc) Characteristic Symbol Min Typ Max Unit Output Voltage I LOAD = 10.0 µA I LOAD = –10.0 µA V OL V OH — V DD– 0.1 — — 0.1 — V Output High Voltage (I LOAD –0.6 mA) Port A, Port B, Port C (1–7) (I LOAD –10.0 mA) IRO (I LOAD –1.2 mA) Port C (Bit 0) V OH V DD– 0.3 V DD– 0.7 V DD– 0.3 V DD– 0.1 V DD– 0.1 V DD– 0.1 — — — V Output Low Voltage (I LOAD = 1.0 mA) Port A, Port B, Port C (1–7) (I LOAD = 8.0 mA) IRO (I LOAD = 7.0 mA) Port C (Bit 0) V OL — — — 0.1 0.1 0.1 0.3 0.8 0.3 V Input High Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 V IH 0.7 x V DD —V DD V Input Low Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 V IL V SS — 0.4 x V DD V EPROM Programming Voltage V 14.5 — 15.5 V Supply Current (see Notes) Run Wait Stop 25 oC 0 to +70 oC I DD — — — — 1.8 0.33 0.1 0.1 3.0 0.8 4.0 8.0 mA mA µA µA I/O Ports Hi-Z Leakage Current Port A, Port B, Port C I OZ –4 — 4 µA Input Current RESET, LPRST, IRQ, OSC1 PB0-PB7 with pullups enabled (VIN = 0.4 x VDD) 8 PB0-PB7 with pullups enabled (VIN = 0.7 x VDD) I IN –0.4 –25 –15 — –80 –50 0.4 –105 –65 µA Capacitance Ports (as Input or Output) RESET, LPRST, IRQ C OUT C INT — — — — 12 8 pF NOTES: 1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TL = 0 °C to +70 °C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25 °C, only represent average measurements. 3. Wait IDD: only core timer active 4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source (fOsc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 5. Wait, Stop IDD: port A and port C configured as inputs, port B configured as outputs. VIL = 0.2 V, VIH = VDD –0.2 V 6. Stop IDD is measured with OSC1 = VSS. 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. Pullups are designed to be capable of pulling to VIH within 25 µs for a 100 pF, 4-kΩ load Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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