HC705V8GRSSLASHD datasheet(137/172 Pages) NXP

137 / 172 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 126

MC68HC705V8 Specification Rev. 2.1

15.5.4.10

Valid SOF Symbol

If the active to passive transition beginning the next data bit or symbol occurs between

and

d, the current symbol would be considered a valid SOF symbol. See Figure 15-14(4).

15.5.4.11

Valid BREAK Symbol

If the next active to passive transition does not occur until after

d, the current symbol will

be considered a valid BREAK symbol. Following the BREAK symbol, an IFS period must

be observed, after which normal communication can resume on the J1805 bus. See Figure

15-14(5).

15.5.5

MESSAGE ARBITRATION

Message arbitration on the J1850 bus is accomplished in a non-destructive manner,

allowing the message with the highest priority to be transmitted, while any transmitters

which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting

again.

If the MDLC wishes to transmit onto the J1850 bus, but detects that another message is in

progress, it must wait until the bus is idle. However, if multiple nodes begin to transmit in

the same synchronization window, message arbitration will occur beginning with the first bit

after the SOF symbol and continue with each bit thereafter.

The VPW symbols and J1850 bus electrical characteristics are carefully chosen so that a

logic zero (active or passive type) will always dominate over a logic one (active or passive

type) simultaneously transmitted. Hence logic zeroes are said to be ’dominant’ and logic

ones are said to be ’recessive’. Whenever a node detects a dominant bit when it transmits

a recessive bit, it loses arbitration, and immediately stops transmitting. This is known as

’bitwise arbitration’.

Figure 15-15:

J1850 VPW Bitwise Arbitration

Transmitter A

Transmitter B

J1850 Bus

SOF

Data

Bit 1

Data

Bit 4

Data

Bit 5

"0"

Transmitter A detects

an active state on

the bus, and stops

transmitting

Transmitter B wins

Passive

Active

Passive

Active

Passive

Active

"0"

"1"

Data

Bit 2

"1"

Data

Bit 3

"0"

"1"

arbitration and

continues

transmitting

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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