HC705V8GRSSLASHD datasheet(101/172 Pages) NXP

101 / 172 page

SECTION 14: SERIAL PERIPHERAL INTERFACE

Page 90

MC68HC705V8 Specification Rev. 2.1

The SPI forces the direction on some of the pin to output in order to function properly.

Figure 14-1:

Data Clock Timing Diagram

14.1.1

Master In Slave Out (MISO/PF3)

The MISO line is configured as an input in a master device and as an output in a slave

device. It is one of the two lines that transfer serial data in one direction, with the most

significant bit sent first. The MISO line of a slave device is placed in the high-impedance

state if the slave is not selected.

14.1.2

Master Out Slave In (MOSI/PF2)

The MOSI line is configured as an output in a master device and as an input in a slave

device. It is one of the two lines that transfer serial data in one direction with the most

significant bit sent first.

14.1.3

Serial Clock (SCK/PF1)

The master clock is used to synchronize data movement both in and out of the device

through its MOSI and MISO lines. The master and slave devices are capable of exchanging

a byte of information during a sequence of eight clock cycles. Since SCK is generated by

the master device, this line becomes an input on a slave device.

As shown in Figure 14-1, four possible timing relationships may be chosen by using control

bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and

slave devices must operate with the same timing. The master device always places data

on the MOSI line a half-cycle before the clock edge (SCK), in order for the slave device to

latch the data.

Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a

slave device, SPR0 and SPR1 have no effect on the operation of the SPI.

INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)

MSB

6543210

SCK

MISO/MOSI

(CPOL=0, CPHA=0)

(CPOL=0, CPHA=1)

(CPOL=1, CPHA=0)

(CPOL=1, CPHA=1)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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