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HC705V8GRS/D Datasheet(PDF) 103 Page - NXP Semiconductors |
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HC705V8GRS/D Datasheet(HTML) 103 Page - NXP Semiconductors |
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103 / 172 page  SECTION 14: SERIAL PERIPHERAL INTERFACE Page 92 MC68HC705V8 Specification Rev. 2.1 Figure 14-2: Serial Peripheral Interface Block Diagram In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again. In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave’s MISO line. Figure 14-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections. DIVIDER ÷2 ÷4 ÷16 ÷32 SELECT 8-BIT SHIFT REG READ DATA BUFF MSB LSB S M M S S M CLOCK CLOCK LOGIC SPI CLOCK MSTR SPE SPI CONTROL REGISTER INTERNAL DATA BUS SPI INTERRUPT REQUEST SPI STATUS REGISTER SPI CONTROL INTERNAL MCU CLOCK PF1/ PF0/ PF2/ PF3/ MISO MOSI SCK SS (MASTER) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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