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ADN2814XCPZ Datasheet(PDF) 5 Page - Analog Devices

Part # ADN2814XCPZ
Description  Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN2814XCPZ Datasheet(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
ADN2814
Rev. PrA | Page 5 of 28
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
LVDS OUPUT CHARACTERISTICS
(CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
VSE (see Figure 3)
250
400
mV
Differential Output Swing
VDIFF (see Figure 3)
500
800
mV
Output Offset Voltage
1125
1200
1275
mV
Output Impedance
Differential
100
Ω
LVDS Ouputs Timing
Rise Time
20% to 80%
TBD
ps
Fall Time
80% to 20%
TBD
ps
Setup Time
TS (see Figure 2), OC12
800
ps
Hold Time
TH (see Figure 2), OC12
800
ps
I2C INTERFACE DC CHARACTERISTICS
LVCMOS
Input High Voltage
VIH
0.7 VCC
V
Input Low Voltage
VIL
0.3 VCC
V
Input Current
VIN = 0.1 VCC or VIN = 0.9 VCC
−10.0
+10.0
µA
Output Low Voltage
VOL, IOL = 3.0 mA
0.4
V
I2C INTERFACE TIMING
(See Figure 10)
SCK Clock Frequency
400
kHz
SCK Pulse Width High
tHIGH
600
ns
SCK Pulse Width Low
tLOW
1300
ns
Start Condition Hold Time
tHD;STA
600
ns
Start Condition Setup Time
tSU;STA
600
ns
Data Setup Time
tSU;DAT
100
ns
Data Hold Time
tHD;DAT
300
ns
SCK/SDA Rise/Fall Time
TR/TF
20 + 0.1 Cb1
300
ns
Stop Condition Setup Time
tSU;STO
600
ns
Bus Free Time between a Stop and a Start
tBUF
1300
ns
REFCLK CHARACTERISTICS
Optional lock to REFCLK mode
Input Voltage Range
@ REFCLKP or REFCLKN
VIL
0
V
VIH
VCC
V
Minimum Differential Input Drive
100
mV p-p
Reference Frequency
12.3
200
MHz
Required Accuracy
100
ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
VIL
0.8
V
Input High Current
IIH, VIN = 2.4 V
5
µA
Input Low Current
IIL, VIN = 0.4 V
−5
µA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
VOH, IOH = −2.0 mA
2.4
V
Output Low Voltage
VOL, IOL = 2.0 mA
0.4
V
1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.



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