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ADN2814XCPZ Datasheet(PDF) 13 Page - Analog Devices

Part # ADN2814XCPZ
Description  Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADN2814XCPZ Datasheet(HTML) 13 Page - Analog Devices

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Preliminary Technical Data
ADN2814
Rev. PrA | Page 13 of 28
JITTER SPECIFICATIONS
The ADN2814 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2814 performance with respect to those specifications.
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms, and must be less than 0.1 UIp-p.
JITTER TRANSFER
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
signal (see Figure 14).
0.1
ACCEPTABLE
RANGE
fC
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
Figure 14. Jitter Transfer Curve
JITTER TOLERANCE
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 15).
15.00
1.50
0.15
f0
f1
f2
f3
f4
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
Figure 15. SONET Jitter Tolerance Mask



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