Preliminary Technical Data

ADN2814

Rev. PrA | Page 11 of 28

Reg Name

R/W

Address

D7

D6

D5

D4

D3

D2

D1

D0

FREQ0

R

0x0

MSB

LSB

FREQ1

R

0x1

MSB

LSB

FREQ2

R

0x2

0

MSB

LSB

RATE

R

0x3

COARSE_RD[8] MSB

Coarse datarate readback

COARSE_RD[1]

MISC

R

0x4

x

x

LOS

status

Static

LOL

LOL

status

Datarate

measure

complete

x

COARSE_

RD[0] LSB

CTRLA

W

0x8

Measure

datarate

Lock to

reference

CTRLB

W

0x9

Config

LOL

Reset

MISC[4]

System

reset

0

Reset

MISC[2]

0

0

0

CTRLC

W

0x11

0

0

0

0

0

Config LOS

Squelch

mode

0

Table 7. Miscellaneous Register, MISC

LOS Status

Static LOL

LOL Status

Datarate Measurement

Complete

Coarse Rate

Readback LSB

D7

D6

D5

D4

D3

D2

D1

D0

x

x

0 = No loss of signal

0 = Waiting for next LOL

0 = Locked

0 = Measuring datarate

x

COARSE_RD[0]

1 = Loss of signal

1 = Static LOL until reset

1 = Acquiring

1 = Measurement complete

Measure Datarate

Lock to Reference

D7

D6

D5

D4

D3

D2

D1

D0

0

0

12.3 MHz to 25 MHz

0

0

0

0

1

Set to 1 to measure datarate

0 = Lock to input data

0

1

25 MHz to 50 MHz

0

0

0

1

2

1 = Lock to reference clock

1

0

50 MHz to 100 MHz

0

0

1

0

4

1

1

100 MHz to 200 MHz

n

1

0

0

0

256

REF

is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).

Table 9. Control Register, CTRLB

Config LOL

Reset MISC[4]

System Reset

Reset MISC[2]

D7

D6

D5

D4

D3

D2

D1

D0

0 = LOL pin normal operation

1 = LOL pin is static LOL

Write a 1 followed by

0 to reset MISC[4]

Write a 1 followed by

0 to reset ADN2814

Set

to 0

Write a 1 followed by

0 to reset MISC[2]

Set

to 0

Set

to 0

Set

to 0

Table 10. Control Register, CTRLC

Config LOS

Squelch Mode

D7

D6

D5

D4

D3

D2

D1

D0

0 = Active high LOS

0 = Squelch CLK and DATA

Set to 0

Set to 0

Set to 0

Set to 0

Set to 0

Set to 0

1 = Active low LOS

1 = Squelch CLK or DATA