ADN2814XCPZ datasheet(16/28 Pages) AD

16 / 28 page

ADN2814

Preliminary Technical Data

Rev. PrA | Page 16 of 28

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2814 acquires frequency from the data over a range of

data frequencies from 12.3 Mb/s to 675 Mb/s. The lock detector

circuit compares the frequency of the VCO and the frequency

of the incoming data. When these frequencies differ by more

than 1000 ppm, LOL is asserted. This initiates a frequency

acquisition cycle. The VCO frequency is reset to the bottom of

its range, which is 12.3 MHz. The frequency detector then

compares this VCO frequency and the incoming data frequency

and increments the VCO frequency, if necessary. Initially, the

VCO frequency is incremented in large steps to aid fast acquisi-

tion. As the VCO frequency approaches the data frequency, the

step size is reduced until the VCO frequency is within 250 ppm

of the data frequency, at which point LOL is de-asserted.

Once LOL is de-asserted, the frequency-locked loop is turned

off. The PLL/DLL pulls in the VCO frequency the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between

CF1 and CF2, Pins 14 and 15. A 0.47 µF ± 20%, X7R ceramic

chip capacitor with < 10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 µF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 uF capacitor should be greater than 300 MΩ.

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN), which

are internally terminated with 50 Ω to an on-chip voltage

reference (VREF = 2.5 V typically). The inputs are typically

ac-coupled externally, although dc coupling is possible as long

as the input common mode voltage remains above 2.5 V (see

Figure 26, Figure 27, and Figure 28 in the Applications

Information section). Input offset is factory trimmed to achieve

better than 6 mV typical sensitivity with minimal drift. The

limiting amplifier can be driven differentially or single-ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of amplified spontaneous emission (ASE) noise or

duty cycle distortion by applying a differential voltage input of

up to ±0.95 V to SLICEP/N inputs. If no adjustment of the slice

level is needed, SLICEP/N should be tied to VEE. The gain of

the slice adjustment is ~0.1 V/V.

LOSS OF SIGNAL (LOS) DETECTOR

The receiver front end LOS detector circuit detects when the

input signal level has fallen below a user-adjustable threshold.

The threshold is set with a single external resistor from Pin 9,

THRADJ, to VEE. The LOS comparator trip point-versus-

resistor value is illustrated in Figure 5. If the input level to the

ADN2814 drops below the programmed LOS threshold, the

output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.

The LOS detector’s response time is ~500 ns by design, but is

dominated by the RC time constant in ac-coupled applications.

The LOS pin defaults to active high. However, by setting Bit

CTRLC[2] to 1, the LOS pin is configured as active low.

There is typically 6 dB of electrical hysteresis designed into the

LOS detector to prevent chatter on the LOS pin. This means

that, if the input level drops below the programmed LOS

threshold causing the LOS pin to assert, the LOS pin is not de-

asserted until the input level has increased to 6 dB (2×) above

the LOS threshold (see Figure 18).

HYSTERESIS

LOS OUTPUT

INPUT LEVEL

LOS THRESHOLD

Figure 18. LOS Detector Hysteresis

The LOS detector and the SLICE level adjust can be used

simultaneously on the ADN2814. This means that any offset

added to the input signal by the SLICE adjust pins does not

affect the LOS detector’s measurement of the absolute input

level.

LOCK DETECTOR OPERATION

The lock detector on the ADN2814 has three modes of

operation: normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2814 is a continuous rate CDR that

locks onto any data rate from 12.3 Mb/s to 675 Mb/s without

the use of a reference clock as an acquisition aid. In this mode,

the lock detector monitors the frequency difference between the

VCO and the input data frequency, and de-asserts the loss of

lock signal, which appears on LOL Pin 16, when the VCO is

within 250 ppm of the data frequency. This enables the D/PLL,

which pulls the VCO frequency in the remaining amount and

also acquires phase lock. Once locked, if the input frequency

error exceeds 1000 ppm (0.1%), the loss of lock signal is re-

asserted and control returns to the frequency loop, which

begins a new frequency acquisition starting at the lowest point

in the VCO operating range, 12.3 MHz. The LOL pin remains

asserted until the VCO locks onto a valid input data stream to

ADN2814XCPZ Datasheet(PDF) 16 Page - Analog Devices

ADN2814XCPZ Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL