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STM32U545NET3QTR Datasheet(PDF) 207 Page - STMicroelectronics |
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STM32U545NET3QTR Datasheet(HTML) 207 Page - STMicroelectronics |
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207 / 283 page ![]() DS14216 Rev 1 207/283 STM32U545xx Electrical characteristics 258 Ilkg (3)(4) Input leakage current TT_xx I/Os except OPAMPx_VINM (x = 1, 2) VIN ≤ Max (VDDXXX)(5) -- 500 nA OPAMPx_VINM (x = 1, 2) dedicated input leakage current -- (7) RPU Weak pull-up equivalent -30 40 50 kΩ RPD Weak pull-down equivalent resistor(8) -30 40 50 CIO I/O pin capacitance -- 5 - pF 1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O. 2. Refer to Figure 34: I/O input characteristics (all I/Os except BOOT0 and FT_c). 3. Specified by design. Not tested in production. 4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg max. 5. Max (VDDXXX) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as described in Table 26: Legend/abbreviations used in the pinout table. 6. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must be disabled. 7. Refer to Ibias in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current. 8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). Table 93. I/O static characteristics(1) (continued) Parameter Conditions Min Typ Max |
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