SLG51002C datasheet(6/36 Pages) RENESAS

6 / 36 page

SLG51002

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switches

Datasheet

Revision 3.1

12-Sep-2022

CFR0011-120-00

6 of 35

Pin No.

Name

Signal

Name

Function

Input Options

Output Options

GPIO2

High voltage General

Purpose IO

Digital Input

with/without Schmitt

trigger, Low voltage

digital input, Ultra-

Low voltage digital

input

Push-Pull, Open-Drain

NMOS, Open-Drain

PMOS

I2C_SA2

I2C Slave address 2

GPIO3

High voltage General

Purpose IO

Digital Input

with/without Schmitt

trigger, Low voltage

digital input, Ultra-

Low voltage digital

input

Push-Pull, Open-Drain

NMOS, Open-Drain

PMOS

I2C_SA3

I2C Slave address 3

GPIO4

High voltage General

Purpose IO

Digital Input

with/without Schmitt

trigger, Low voltage

digital input, Ultra-

Low voltage digital

input

Push-Pull, Open-Drain

NMOS, Open-Drain

PMOS

I2C_SA4

I2C Slave address 4

GPIO5

1.2 V/1.8 V input cell,

Low voltage General

Purpose IO

Digital Input

Open-Drain NMOS

SDA

1.2 V/1.8 V input cell,

I2C Serial Data Line

(SDA)

Digital Input

Open-Drain NMOS

GPI6

1.2 V/1.8 V input cell,

Low voltage General

purpose input

Digital Input

SCL

1.2 V/1.8 V input cell,

I2C Serial Clock Line

(SCL)

Digital Input

VIN1_2

Controller and power

FET supply voltage for

LDO1 and LDO2.

VIN3

Controller and power

FET supply voltage for

LDO3.

VIN4

Controller and power

FET supply voltage for

LDO4.

VIN5

Controller and power

FET supply voltage for

LDO5.

SLG51002C Datasheet(PDF) 6 Page - Renesas Technology Corp

SLG51002C Datasheet(HTML) 6 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL