PowerPC 604 RISC Microprocessor Technical Summary

29

1.3.5 Instruction Timing

As shown in Figure 7, the common pipeline of the 604 has six stages through which all instructions must

pass. Some instructions occupy multiple stages simultaneously and some individual execution units have

additional stages. For example, the floating-point pipeline consists of three stages through which all

floating-point instructions must pass.

Floating-point

assist

00E00

Defined by the PowerPC architecture, but not required in the 604.

Reserved

00E10–00EFF

—

Performance

monitoring

interrupt

00F00

The performance monitoring interrupt is a 604-specific excepting and is used

with the 604 performance monitor, described in Section 1.5, “Performance

Monitor.”

The performance monitoring facility can be enabled to signal an exception

when the value in one of the performance monitor counter registers (PMC1 or

PMC2) goes negative. The conditions that can cause this exception can be

enabled or disabled in the monitor mode control register 0 (MMCR0).

Although the exception condition may occur when the MSR EE bit is cleared,

the actual interrupt is masked by the EE bit and cannot be taken until the EE bit

is set.

Reserved

01000–012FF

—

Instruction

address

breakpoint

01300

An instruction address breakpoint exception occurs when the address (bits 0 to

29) in the IABR matches the next instruction to complete in the completion unit,

and the IABR enable bit (bit 30) is set to 1.

System

management

interrupt

01400

A system management interrupt is caused when MSR[EE] = 1 and the SMI

input signal is asserted. This exception is provided for use with the nap mode,

which is described in Section 1.4, “Power Management—Nap Mode.”

Reserved

01500-02FFF

—

Reserved

01000–02FFF

Reserved, implementation-specific exceptions. These are not implemented in

the 604.

Table 3. Exceptions and Conditions (Continued)

Exception

Type

Vector Offset

(hex)

Causing Conditions

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