MPC604/D

(Motorola Order Number)

5/94

REV 1

MPR604TSU-02

(IBM Order Number)

PowerPC, PowerPC Architecture, POWER Archiitecture, and PowerPC 604 are trademarks of International Business Machines Corp.

This document contains information on a new product under development. Specifications and information herein are subject to change without notice.

© Motorola Inc. 1994

Instruction set and other portions hereof

© International Business Machines Corp. 1991–1994

™

Advance Information

PowerPC™ 604 RISC Microprocessor

Technical Summary

This document provides an overview of the PowerPC 604

™ microprocessor. It includes

the following:

•

An overview of 604 features

•

Details about the 604 hardware implementation. This includes descriptions of the

604’s execution units, cache implementation, memory management units

(MMUs), and system interface.

•

A description of the 604 execution model. This section includes information about

the programming model, instruction set, exception model, and instruction timing.

In this document, the terms “PowerPC 604 Microprocessor” and “604” are used to denote

a microprocessor from the PowerPC Architecture

™ family.

1.1 Overview

This section describes the features of the 604, provides a block diagram showing the major

functional units, and describes briefly how those units interact.

The 604 is an implementation of the PowerPC family of reduced instruction set computer

(RISC) microprocessors. The 604 implements the PowerPC architecture as it is specified

for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data

types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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