PowerPC 604 RISC Microprocessor Technical Summary

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The execution unit reports any internal exceptions to the completion stage and continues execution,

regardless of the exception. Under some circumstances, results can be written directly to the target

registers, bypassing the rename buffers.

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Complete (C)—The completion stage ensures that the correct machine state is maintained by

monitoring instructions in the completion buffer and the status of instruction in the execute stage.

When instructions complete, they are removed from the reorder buffer (ROB). Results may be

written back from the rename buffers to the register as early as the complete stage. If the completion

logic detects an instruction containing exception status or if a branch has been mispredicted, all

subsequent instructions are cancelled, any results in rename buffers are discarded, and instructions

are fetched from the correct instruction stream.

The CR, CTR, and LR are also updated during the complete stage.

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Writeback (W)—The writeback stage is used to write back any information from the rename buffers

that was not written back during the complete stage.

All instructions are fully pipelined except for divide operations and some integer multiply operations. The

integer multiplier is a three-stage pipeline. Integer divide instructions iterate in stage two of the multiplier.

SPR operations can execute in the MCIU in parallel with multiply and divide operations.

The floating-point pipeline has three stages. Floating-point divide operations iterate in the first stage.

1.4 Power Management—Nap Mode

The 604 provides a power-saving mode, called nap mode, in which all internal processing and bus operation

is suspended. Software initiates nap mode by setting the MSR[POW] bit. After this bit is set, the 604

suspends instruction dispatch and waits for all activity in progress, including active and pending bus

transactions, to complete. It then powers down the internal clocks, and indicates nap mode by asserting the

HALTED output signal.

When the 604 is in nap mode, all internal activity stops except for decrementer, time base, and interrupt

logic, and the 604 does not snoop bus activity unless the system asserts the RUN input signal. Asserting the

RUN signal causes the HALTED signal to be negated.

Nap mode is exited (clocks resume and MSR[POW] cleared) when any asynchronous interrupt is detected.

1.5 Performance Monitor

The 604 incorporates a performance monitor facility that system designers can use to help bring up, debug,

and optimize software performance, especially in multiprocessing systems. The performance monitor is a

software-accessible mechanism that provides detailed information concerning the dispatch, execution,

completion, and memory access of PowerPC instructions.

The performance monitor control register (MMCR0) can be used to specify the conditions for which a

performance monitoring interrupt is taken. For example, one such condition is associated with one of the

counter registers (PMC1 or PMC2) incrementing until the most significant bit indicates a negative value.

Additionally. the sampled instruction address and sampled data address registers (SIA and SDA) are used

to hold addresses for instruction and data related to the performance monitoring interrupt.

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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