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PowerPC 604 RISC Microprocessor Technical Summary

1.2.5.1 Memory Accesses

Memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock cycle. Data

transfers occur in either single-beat transactions or four-beat burst transactions. A single-beat transaction

transfers as much as 64 bits. Single-beat transactions are caused by noncached accesses that access memory

directly (that is, reads and writes when caching is disabled, cache-inhibited accesses, and stores in write-

through mode). Burst transactions, which always transfer an entire cache block (32 bytes), are initiated

when a block in the cache is read from or written to memory. Additionally, the 604 supports address-only

transactions used to invalidate entries in other processors’ TLBs and caches.

Typically I/O accesses are performed using the same protocol as memory accesses.

1.2.5.2 Signals

The 604’s signals are grouped as follows:

•

Address arbitration signals—The 604 uses these signals to arbitrate for address bus mastership.

•

Address transfer start signals—These signals indicate that a bus master has begun a transaction on

the address bus.

•

Address transfer signals—These signals, which consist of the address bus, address parity, and

address parity error signals, are used to transfer the address and to ensure the integrity of the

transfer.

•

Transfer attribute signals—These signals provide information about the type of transfer, such as the

transfer size and whether the transaction is bursted, write-through, or cache-inhibited.

•

Address transfer termination signals—These signals are used to acknowledge the end of the address

phase of the transaction. They also indicate whether a condition exists that requires the address

phase to be repeated.

•

Data arbitration signals—The 604 uses these signals to arbitrate for data bus mastership.

•

Data transfer signals—These signals, which consist of the data bus, data parity, and data parity error

signals, are used to transfer the data and to ensure the integrity of the transfer.

•

Data transfer termination signals—Data termination signals are required after each data beat in a

data transfer. In a single-beat transaction, the data termination signals also indicate the end of the

tenure, while in burst accesses, the data termination signals apply to individual beats and indicate

the end of the tenure only after the final data beat. They also indicate whether a condition exists that

requires the data phase to be repeated.

•

System status signals—These signals include the interrupt signal, checkstop signals, and both soft-

and hard-reset signals. These signals are used to interrupt and, under various conditions, to reset the

processor.

•

Processor state signals—These two signals are used to set the reservation coherency bit and set the

size of the 604’s output buffers.

•

Miscellaneous signals—These signals are used in conjunction with such resources as secondary

caches and the time base facility.

•

COP interface signals—The common on-chip processor (COP) unit is the master clock control unit

and it provides a serial interface to the system for performing built-in self test (BIST).

•

Clock signals—These signals determine the system clock frequency. These signals can also be used

to synchronize multiprocessor systems.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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