MPC603ECSLASHD datasheet(6/31 Pages) NXP

6 / 31 page

603 Hardware Specifications

Table 5 provides the power consumption for the 603.

Output low voltage, IOL = 14 mA

VOL

—

0.4

Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY)Cin

—

10.0

Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY)Cin

—

15.0

Notes:

1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK), and JTAG signals.

2. Capacitance is periodically sampled rather than 100% tested.

Table 5. Power Consumption

Vdd = 3.3

± 5% V dc, GND = 0 V dc, 0 ≤ T

j ≤ 105 °C

CPU Clock:

SYSCLK

Processor Core Frequency

Unit

66.67 MHz

80 MHz

Full-On Mode

Typical

Maximum

1.8

2.0

2.5

2.9

Doze Mode*

Typical

740

800

Nap Mode*

Typical

160

Sleep Mode*

Typical

125

130

Sleep Mode—PLL Disabled*

Typical

Sleep Mode—PLL and SYSCLK Disabled*

Typical

Note: These values apply for all valid PLL_CFG[0–3] settings and do not include

output driver power (OVdd) or analog supply power (AVdd). OVdd power is

system dependent but is typically

≤ 10% of Vdd. Worst-case AVdd = 15 mW.

Table 4. DC Electrical Specifications (Continued)

Vdd = 3.3

± 5% V dc, GND = 0 V dc, 0 ≤ T

j ≤ 105 °C

Characteristic

Symbol

Min

Max

Unit

Notes

IVE

D B

Y F

INC

MPC603EC/D Datasheet(PDF) 6 Page - NXP Semiconductors

MPC603EC/D Datasheet(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL