ADF7021 datasheet(22/44 Pages) AD

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ADF7021

Preliminary Technical Data

Rev. PrI | Page 22 of 44

Internal AFC

The ADF7021 supports a real-time, internal, automatic

frequency control loop. In this mode, an internal control loop

automatically monitors the frequency error and adjusts the

synthesizer-N divider using an internal PI control loop.

The internal AFC control loop parameters are controlled in

R10_DB4 to 1. A scaling coefficient must also be entered, based

on the crystal frequency in use. This is set up in R10_DB[5:16]

and should be calculated using

AFC_Scaling_Coefficient = (500 × 224)/XTAL

Maximum AFC Range

The maximum AFC frequency range is ±127.5 kHz. This is set

by Bits R10_DB[24:31]. The maximum AFC pull-in range

should be less than or equal to half the channel spacing to

prevent the AFC pulling in a signal in the adjacent channel. If

the maximum AFC pull-in range is larger than the IF filter

bandwidth, the attenuation of the IF filter must be considered.

When AFC errors have been removed using either the internal

or external AFC, further improvement in the receiver’s sensi-

tivity can be obtained by reducing the IF filter bandwidth using

Bits R4_DB[30:31].

AUTOMATIC SYNC WORD RECOGNITION

The ADF7021 also supports automatic detection of the sync or

ID fields. To activate this mode, the sync (or ID) word must be

preprogrammed into the ADF7021. In receive mode, this

preprogrammed word is compared to the received bit stream,

and when a valid match is identified, the external SWD pin is

asserted by the ADF7021 on the next Rx clock pulse.

This feature can be used to alert the microprocessor that a valid

channel has been detected. It relaxes the computational require-

ments of the microprocessor and reduces the overall power

consumption.

The SWD signal can also be used to frame a received packet

length by staying high for a preprogrammed number of bytes.

The data packet length can be set in Bits R12_DB[8:15].

The SWD pin status can be configured by setting Bits

R12_DB[6:7]. Bits R11_DB[4:5] are used to set the length of the

sync/ID word, which can be 12, 16, 20, or 24 bits long. The

transmitter must transmit the MSB of the sync byte first and the

LSB last to ensure proper alignment in the receiver sync-byte-

detection hardware.

For systems using FEC, an error tolerance parameter can also

be programmed that accepts a valid match when up to 3 bits of

the word are incorrect. The error tolerance value is assigned in

R11_DB[6:7].

ADF7021 Datasheet(PDF) 22 Page - Analog Devices

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