1112F—02/27/09

ICS9LP505-1

64-pin CK505 for Desktop Systems

IDT® 64-pin CK505 for Desktop Systems

10

Intentional PCI Clock to Clock Delay

200 ps nominal steps

PCI0

PCI1

PCI2

PCI3

PCI4

PCI_F5

1.0ns

Electrical Characteristics - PCICLK/PCICLK_F

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

NOTES

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

1,2

33.33MHz output no spread

29.99700

30.00300

ns

2

33.33MHz output spread

30.08421

30.23459

ns

2

33.33MHz output no spread

29.49700

30.50300

ns

2

33.33MHz output nominal/spread

29.56617

30.58421

ns

2

Rising Edge Slew Rate

t

SLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

t

FLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Pin to Pin Skew

t

skew

V

T = 1.5 V

250

ps

2

Intential PCI to PCI delay

t

skew

V

T = 1.5 V

100

200

ps

2

Duty Cycle

d

t1

V

T = 1.5 V

45

55

%

2

Jitter, Cycle to cycle

t

jcyc-cyc

V

T = 1.5 V

500

ps

2

Clock period

T

period

T

abs

Absolute min/max period

Electrical Characteristics - USB48MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

NOTES

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

2,4

Clock period

T

period

48.00MHz output nominal

20.83125

20.83542

ns

2,3

Absolute min/max period

T

abs

48.00MHz output nominal

20.48125

21.18542

ns

2

CLK High Time

T

HIGH

8.216563

11.15198

V

CLK Low time

T

LOW

7.816563

10.95198

V

Rising Edge Slew Rate

t

SLR

Measured from 0.8 to 2.0 V

1

2

V/ns

1

Falling Edge Slew Rate

t

FLR

Measured from 2.0 to 0.8 V

1

2

V/ns

1

Duty Cycle

d

t1

V

T = 1.5 V

45

55

%

2

Jitter, Cycle to cycle

t

jcyc-cyc

V

T = 1.5 V

350

ps

2

Electrical Characteristics - REF-14.318MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

2, 4

Clock period

T

period

14.318MHz output nominal

69.82033

69.86224

ns

2, 3

Absolute min/max period

T

abs

14.318MHz output nominal

69.83400

70.84800

ns

2

CLK High Time

T

HIGH

29.97543

38.46654

V

CLK Low time

T

LOW

29.57543

38.26654

V

Rising Edge Slew Rate

t

SLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

t

FLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Duty Cycle

d

t1

V

T = 1.5 V

45

55

%

2

Jitter, Cycle to cycle

t

jcyc-cyc

V

T = 1.5 V

1000

ps

2

1Edge rate in system is measured from 0.8V to 2.0V.

2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V

3 The average period over any 1us period of time

4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz

NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).