MPC821 datasheet(37/242 Pages) NXP

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Functional Description

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

be shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear address-

ing scheme is not a must, than only minimal multiplexing is required to support variable port width.

In TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, the FADS’s dram address connection

scheme is presented:

As can seen from the table above, most of the address lines remain fixed while only 2 lines (the

shaded cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines’

Switching Scheme" on page 35. The switches on that figure are implemented by active multiplexers

controlled by the BCSR1/Dram_Half_Word* bit.

FIGURE 4-2 DRAM Address Lines’ Switching Scheme

TABLE 4-4. DRAM ADDRESS CONNECTIONS

Width

32 - Bit

16 - Bit

Depth

Dram ADD

4 M

1 M

4 M

1 M

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA30

A10

BA19

BA30

A(0:8)

A10

BA(21:29)

BA20

BA30

BA19

BA30

DRAM

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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