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MPC821 Datasheet(PDF) 74 Page - NXP Semiconductors |
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MPC821 Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 242 page  Support Information MPC8XXFADS Design Specification—Rev 0.1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE A•1 U2 - Debug Port Controller "****************************************************************************** "****************************************************************************** "* MPC8XX FADS Debug Port Controller. * "* Mach controller for an interface between Sun ADI port at one side, to * "* debug port at the other. * "****************************************************************************** "* In this file (8): "* - Added support for VFLS / FRZ switching, for both normal operation and "* external debug station connected to the FADS. "* Support includes: "* - separating vfls between MPC and debug port. "* - Selection between frz / vfls (default) is done by VflsFrz~ input pin. "* - Selection between on-board / off-board vfls/frz is done by ChinS~ coming "* from the expansion connectors. "* - VFLS(0:1) are driven towards the debug-port connector when board is not "* selected, i.e., either ADI is disconnected or addresses don't match. "****************************************************************************** "* In this file (7): "* - BundleDelay field in the control register is changed to debug port "* clock frquency select according to the following values: "* 0 - divide by 8 (1.25 Mhz) "* 1 - divide by 4 (2.5 Mhz) "* 2 - divide by 2 (5 Mhz) "* 3 - divide by 1 (10 Mhz) default. "* - Added clock divider for 2 , 4, 8 output of which is routed externaly "* to the i/f clock input. "****************************************************************************** "* In this file (6): "* - RUN siganl polarity was changed to active-high, this, to support "* other changes for revision PILOT of the fads. "****************************************************************************** "* In this file (5) added: "* - protection against spikes on the reset lines, so that the interface "* will not be reset by an accidental spike. "* - D_C~ signal was synchronized to avoid accidental write to control "* during data write. "* - DSDI is given value (H) prior to negation of SRESET* to comply with 5XX "* family "****************************************************************************** "* In this file (4) the polarity of address selection lines is reversed so Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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