MPC821 datasheet(95/242 Pages) NXP

95 / 242 page

Support Information

MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

"* Control register bits description:

"* DebugEntry~: (Bit 0). When this bit is active (L), the MPC8XX will enter debug

mode immediately after reset, i.e., DSCK will be held high

after the rising edge of SRESET*. When negated, DSCK will be

held low after the rising edge of SRESET so the MPC8XX will start

running instantly.

"* DiagLoopBack~: (Bit 1). When active (L), the interface is in Diagnostic

Loopback mode. I.e., the source for the Rx shift register is

the output of the Tx shift register. During that mode, DSCK

and DSDI are tri-stated, so no arbitrary data is sent to the

debug port. When inactive, the interface is in normal mode,

i.e., DSCK and DSDI are driven and the source of the Rx shift

"* StatusRequest~: (Bit 2). When active (L) any write to the control register

will be followed by a status read cycle initiated by the

debug port controller, i.e., AdsReq will be asserted after

the write cycle ends. When inactive, a write to the control

"* DbgClkDivSel(1:0) : (Bits 4,3). This field selects the division of the

DbgClk input. Division factors are set as follows:

0 - by 1

1 - by 2

2 - by 4

3 - by 8

"* Important!!! All bits wake up active (L) after reset.

"******************************************************************************

equations

AdiCtrlReg.clk = IClk;

AdiCtrlReg.ar = Reset;"All active low.

when ( HOST_WRITE_ADI_CONTROL & BndTmrExp.fb) then

AdiCtrlReg.d = [PD4.pin, PD3.pin, PD2.pin, PD1.pin, PD0.pin];

else

AdiCtrlReg.d = AdiCtrlReg.fb;

"******************************************************************************

"* ADI Data Bus.

"* The Adi data bus is driven towards the host when the host reads the i/f.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC821 Datasheet(PDF) 95 Page - NXP Semiconductors