TMPR4955AF datasheet(120/168 Pages) TOSHIBA

120 / 168 page

Chapter 6 TX4955A System Interface

6-48

6.3.9

Processor Read Request

A processor read request is issued by the following:

•

driving a read command on the SysCmd bus

•

driving a read address on the SysAD bus

•

asserting PValid

PValid

PValid*

Only one processor read request may be pending at a time. The processor must wait for

an external read response before starting a subsequent read.

The processor moves to slave state after the issue cycle of the read request, by

deasserting the PMaster

PMaster

PMaster* signal. An external agent may then return the requested data

through a read response. The external agent, which is now bus master, may issue any

number of writes before sending the read response data.

An example of a processor read request and an uncompelled change to slave state

occurring as the read request is issued is illustrated in Figure 6.3.17.

Read

Addr

812

611

SysAD

SCycle

SClock

SysCmd

EOK*

PValid*

PMaster*

Figure 6.3.17 Processor Read Request

The TX4955A support the Read Time Out Function. This Function is when the retern

data wait but the time out counter. See chapter 6.3.20 Mode Register of System Interface

(G2SConfig).

6.3.10

External Write Request

External write requests are similar to a processor single write except that the signal

EValid is asserted instead of the signal PValid

PValid

PValid*. An external write request consists of the

following:

•

an external agent driving a write command on the SysCmd bus and a write

address on the SysAD bus

•

asserting EValid

EValid

EValid* for one cycle

•

driving a data identifier on the SysCmd bus and data on the SysAD bus

•

asserting EValid

EValid

EValid* for one cycle.

The data identifier associated with the data cycle must contain a last data cycle

indication. Note that the external agent must gain and maintain bus mastership during

these transactions (see EReq

EReq

EReq* in the Timing Summary, earlier in this chapter).

An external write request example with the processor initially in master state is

illustrated in Figure 6.3.18.

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