TMPR4955AF datasheet(122/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-50

6.3.11

External Read Response

An external agent returns data to the processor in response to a processor read request

by waiting for the processor to move to slave state. The external agent then returns the

data through either a single data cycle or a series of data cycles sufficient to transmit the

requested data. After the last data cycle is issued, the read response is complete and the

processor becomes master (assuming EReq

EReq

EReq* was not asserted).

If, at the end of the read response cycles, EReq

EReq

EReq* has been asserted, the processor remains

in slave state until the external agent relinquishes the bus. When the processor is in slave

state and needs access to the SysAD bus, it waits until EReq

EReq

EReq* is deasserted.

The data identifier associated with a data cycle may indicate that the data transmitted

during that cycle is erroneous; however, an external agent must return a block of data of

the correct size regardless of this erroneous data cycle indication. If a read response

includes one or more erroneous data cycles, the processor takes a bus error.

Read response data must only be delivered to the processor when a processor read

request is pending. The state of the processor is undefined if a read response is presented to

it when no processor read is pending.

An example of a processor single read request followed by a read response is illustrated

in Figure 6.3.19.

EOD

Data

Read

Addr

812

SysAD

SCycle

SClock

SysCmd

EOK

EValid

PValid

PMaster

Figure 6.3.19 Single Read Request Followed By Read Response

A read response example for a processor block read with the system interface already in

slave state is illustrated in Figure 6.3.20.

Data 3

Data 2

Data 1

Data 0

EOD

Data

812

SysAD

SCycle

SClock

SysCmd

EValid*

PValid*

PMaster*

Figure 6.3.20 Block Read Response, System Interface Already In Slave State

TMPR4955AF Datasheet(PDF) 122 Page - Toshiba Semiconductor

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