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DSPIC30F Datasheet(PDF) 212 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 212 Page - Microchip Technology |
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212 / 220 page  dsPIC30F5011/5013 DS70116C-page 210 Preliminary 2004 Microchip Technology Inc. Write Back................................................................... 18 Data Address Space ........................................................... 25 Alignment .................................................................... 28 Alignment (Figure) ...................................................... 28 Effect of Invalid Memory Accesses (Table)................. 28 MCU and DSP (MAC Class) Instructions Example..... 27 Memory Map ......................................................... 25, 26 Near Data Space ........................................................ 29 Software Stack ............................................................ 29 Spaces ........................................................................ 28 Width ........................................................................... 28 Data Converter Interface (DCI) Module ............................ 117 Data EEPROM Memory ...................................................... 51 Erasing ........................................................................ 52 Erasing, Block ............................................................. 52 Erasing, Word ............................................................. 52 Protection Against Spurious Write .............................. 55 Reading....................................................................... 51 Write Verify ................................................................. 55 Writing ......................................................................... 53 Writing, Block .............................................................. 54 Writing, Word .............................................................. 53 DC Characteristics ............................................................ 166 BOR .......................................................................... 177 Brown-out Reset ....................................................... 176 I/O Pin Input Specifications ....................................... 174 I/O Pin Output Specifications .................................... 175 Idle Current (IIDLE) .................................................... 170 Low-Voltage Detect................................................... 175 LVDL ......................................................................... 176 Operating Current (IDD)............................................. 167 Power-Down Current (IPD) ........................................ 172 Program and EEPROM............................................. 177 Temperature and Voltage Specifications .................. 166 DCI Module Bit Clock Generator................................................... 121 Buffer Alignment with Data Frames .......................... 122 Buffer Control ............................................................ 117 Buffer Data Alignment ............................................... 117 Buffer Length Control ................................................ 122 COFS Pin .................................................................. 117 CSCK Pin .................................................................. 117 CSDI Pin ................................................................... 117 CSDO Mode Bit ........................................................ 123 CSDO Pin ................................................................. 117 Data Justification Control Bit ..................................... 121 Device Frequencies for Common Codec CSCK Frequencies (Table)............................... 121 Digital Loopback Mode ............................................. 123 Enable ....................................................................... 119 Frame Sync Generator ............................................. 119 Frame Sync Mode Control Bits ................................. 119 I/O Pins ..................................................................... 117 Interrupts ................................................................... 123 Introduction ............................................................... 117 Master Frame Sync Operation .................................. 119 Operation .................................................................. 119 Operation During CPU Idle Mode ............................. 124 Operation During CPU Sleep Mode .......................... 124 Receive Slot Enable Bits........................................... 122 Receive Status Bits ................................................... 123 Register Map............................................................. 125 Sample Clock Edge Control Bit................................. 121 Slave Frame Sync Operation .................................... 120 Slot Enable Bits Operation with Frame Sync ............ 122 Slot Status Bits ......................................................... 123 Synchronous Data Transfers .................................... 122 Timing Characteristics AC-Link Mode ................................................... 190 Multichannel, I2S Modes................................... 188 Timing Requirements AC-Link Mode ................................................... 190 Multichannel, I2S Modes................................... 189 Transmit Slot Enable Bits ......................................... 121 Transmit Status Bits.................................................. 123 Transmit/Receive Shift Register ............................... 117 Underflow Mode Control Bit...................................... 123 Word Size Selection Bits .......................................... 119 Demonstration Boards PICDEM 1................................................................. 162 PICDEM 17............................................................... 162 PICDEM 18R ............................................................ 163 PICDEM 2 Plus......................................................... 162 PICDEM 3................................................................. 162 PICDEM 4................................................................. 162 PICDEM LIN ............................................................. 163 PICDEM USB ........................................................... 163 PICDEM.net Internet/Ethernet .................................. 162 Development Support ....................................................... 159 Device Configuration Register Map ............................................................ 149 Device Configuration Registers FBORPOR ................................................................ 147 FGS .......................................................................... 147 FOSC........................................................................ 147 FWDT ....................................................................... 147 Device Overview................................................................... 5 Disabling the UART ............................................................ 99 Divide Support .................................................................... 14 Instructions (Table) ..................................................... 14 DSP Engine ........................................................................ 15 Multiplier ..................................................................... 17 Dual Output Compare Match Mode .................................... 82 Continuous Pulse Mode.............................................. 82 Single Pulse Mode...................................................... 82 E Electrical Characteristics .................................................. 165 AC............................................................................. 178 DC ............................................................................ 166 Enabling and Setting Up UART Alternate I/O ............................................................... 99 Setting Up Data, Parity and Stop Bit Selections ......... 99 Enabling the UART ............................................................. 99 Equations A/D Conversion Clock............................................... 129 Baud Rate................................................................. 101 Bit Clock Frequency.................................................. 121 COFSG Period.......................................................... 119 Serial Clock Rate ........................................................ 94 Time Quantum for Clock Generation ........................ 111 Errata .................................................................................... 4 Evaluation and Programming Tools.................................. 163 Exception Sequence Trap Sources .............................................................. 41 External Clock Timing Characteristics Type A, B and C Timer ............................................. 184 External Clock Timing Requirements ............................... 179 Type A Timer ............................................................ 184 Type B Timer ............................................................ 185 Type C Timer ............................................................ 185 |
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