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DSPIC30F Datasheet(PDF) 214 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 214 Page - Microchip Technology |
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214 / 220 page  dsPIC30F5011/5013 DS70116C-page 212 Preliminary 2004 Microchip Technology Inc. Phase Locked Loop (PLL) ................................ 139 Start-up Timer (OST) ........................................ 138 Operating Modes (Table) .......................................... 136 System Overview ...................................................... 135 Oscillator Selection ........................................................... 135 Oscillator Start-up Timer Timing Characteristics .............................................. 182 Timing Requirements ................................................ 183 Output Compare Interrupts ................................................. 83 Output Compare Module ..................................................... 81 Register Map............................................................... 84 Timing Characteristics .............................................. 186 Timing Requirements ................................................ 186 Output Compare Operation During CPU Idle Mode ............ 83 Output Compare Sleep Mode Operation............................. 83 P Packaging Information ...................................................... 205 Marking ..................................................................... 205 Peripheral Module Disable (PMD) Registers .................... 148 PICkit 1 Flash Starter Kit................................................... 163 PICSTART Plus Development Programmer ..................... 161 Pinout Descriptions ............................................................... 8 PLL Clock Timing Specifications....................................... 180 POR. See Power-on Reset. Port Write/Read Example.................................................... 58 PORTA Register Map for dsPIC30F5013 ................................ 59 PORTB Register Map for dsPIC30F5011/5013 ....................... 59 PORTC Register Map for dsPIC30F5011 ................................ 59 Register Map for dsPIC30F5013 ................................ 59 PORTD Register Map for dsPIC30F5011 ................................ 60 Register Map for dsPIC30F5013 ................................ 60 PORTF Register Map for dsPIC30F5011 ................................ 60 Register Map for dsPIC30F5013 ................................ 60 PORTG Register Map for dsPIC30F5011/5013 ....................... 60 Power Saving Modes ........................................................ 146 Idle ............................................................................ 147 Sleep ......................................................................... 146 Sleep and Idle ........................................................... 135 Power-Down Current (IPD) ................................................ 172 Power-up Timer Timing Characteristics .............................................. 182 Timing Requirements ................................................ 183 PRO MATE II Universal Device Programmer ................... 161 Program Address Space ..................................................... 21 Construction ................................................................ 22 Data Access from Program Memory Using Program Space Visibility........................... 24 Data Access From Program Memory Using Table Instructions ..................................... 23 Data Access from, Address Generation...................... 22 Data Space Window into Operation ............................ 25 Data Table Access (LS Word) .................................... 23 Data Table Access (MS Byte) ..................................... 24 Memory Map ............................................................... 21 Table Instructions TBLRDH.............................................................. 23 TBLRDL .............................................................. 23 TBLWTH ............................................................. 23 TBLWTL.............................................................. 23 Program and EEPROM Characteristics............................ 177 Program Counter ................................................................ 12 Programmable .................................................................. 135 Programmer’s Model .......................................................... 12 Diagram ...................................................................... 13 Programming Operations.................................................... 47 Algorithm for Program Flash....................................... 47 Erasing a Row of Program Memory............................ 47 Initiating the Programming Sequence......................... 48 Loading Write Latches ................................................ 48 Protection Against Accidental Writes to OSCCON ........... 140 R Reset ........................................................................ 135, 141 BOR, Programmable ................................................ 143 Brown-out Reset (BOR)............................................ 135 Oscillator Start-up Timer (OST) ................................ 135 POR Operating without FSCM and PWRT................ 143 With Long Crystal Start-up Time ...................... 143 POR (Power-on Reset)............................................. 141 Power-on Reset (POR)............................................. 135 Power-up Timer (PWRT) .......................................... 135 Reset Sequence ................................................................. 41 Reset Sources ............................................................ 41 Reset Sources Brown-out Reset (BOR).............................................. 41 Illegal Instruction Trap ................................................ 41 Trap Lockout............................................................... 41 Uninitialized W Register Trap ..................................... 41 Watchdog Time-out .................................................... 41 Reset Timing Characteristics............................................ 182 Reset Timing Requirements ............................................. 183 Run-Time Self-Programming (RTSP) ................................. 45 S Simple Capture Event Mode ............................................... 77 Buffer Operation ......................................................... 78 Hall Sensor Mode ....................................................... 78 Prescaler .................................................................... 77 Timer2 and Timer3 Selection Mode............................ 78 Simple OC/PWM Mode Timing Requirements ................. 187 Simple Output Compare Match Mode ................................ 82 Simple PWM Mode ............................................................. 82 Input Pin Fault Protection ........................................... 82 Period ......................................................................... 83 Software Simulator (MPLAB SIM) .................................... 160 Software Simulator (MPLAB SIM30) ................................ 160 Software Stack Pointer, Frame Pointer .............................. 12 CALL Stack Frame ..................................................... 29 SPI Module ......................................................................... 85 Framed SPI Support ................................................... 85 Operating Function Description .................................. 85 Operation During CPU Idle Mode ............................... 87 Operation During CPU Sleep Mode............................ 87 SDOx Disable ............................................................. 85 Slave Select Synchronization ..................................... 87 SPI1 Register Map...................................................... 88 SPI2 Register Map...................................................... 88 Timing Characteristics Master Mode (CKE = 0).................................... 191 Master Mode (CKE = 1).................................... 192 Slave Mode (CKE = 1).............................. 193, 194 Timing Requirements Master Mode (CKE = 0).................................... 191 Master Mode (CKE = 1).................................... 192 |
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