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DSPIC30F Datasheet(PDF) 215 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 215 Page - Microchip Technology |
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215 / 220 page  2004 Microchip Technology Inc. Preliminary DS70116C-page 213 dsPIC30F5011/5013 Slave Mode (CKE = 0) ...................................... 193 Slave Mode (CKE = 1) ...................................... 195 Word and Byte Communication .................................. 85 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 1 ..................... 144 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 2 ..................... 145 Status Register ................................................................... 12 Symbols Used in Opcode Descriptions............................. 152 System Integration ............................................................ 135 Register Map............................................................. 149 T Table Instruction Operation Summary ................................ 45 Temperature and Voltage Specifications AC ............................................................................. 178 DC............................................................................. 166 Timer1 Module .................................................................... 63 16-bit Asynchronous Counter Mode ........................... 63 16-bit Synchronous Counter Mode ............................. 63 16-bit Timer Mode ....................................................... 63 Gate Operation ........................................................... 64 Interrupt....................................................................... 64 Operation During Sleep Mode .................................... 64 Prescaler..................................................................... 64 Real-Time Clock ......................................................... 64 Interrupts............................................................. 65 Oscillator Operation ............................................ 65 Register Map............................................................... 66 Timer2 and Timer3 Selection Mode .................................... 82 Timer2/3 Module ................................................................. 67 16-bit Timer Mode ....................................................... 67 32-bit Synchronous Counter Mode ............................. 67 32-bit Timer Mode ....................................................... 67 ADC Event Trigger...................................................... 70 Gate Operation ........................................................... 70 Interrupt....................................................................... 70 Operation During Sleep Mode .................................... 70 Register Map............................................................... 71 Timer Prescaler........................................................... 70 Timer4/5 Module ................................................................. 73 Register Map............................................................... 75 Timing Characteristics A/D Conversion Low-speed (ASAM = 0, SSRC = 000) .............. 203 Bandgap Start-up Time............................................. 183 CAN Module I/O........................................................ 200 CLKOUT and I/O....................................................... 181 DCI Module AC-Link Mode ................................................... 190 Multichannel, I2S Modes ................................... 188 External Clock........................................................... 178 I2C Bus Data Master Mode ..................................................... 196 Slave Mode ....................................................... 198 I2C Bus Start/Stop Bits Master Mode ..................................................... 196 Slave Mode ....................................................... 198 Input Capture (CAPX) ............................................... 186 OC/PWM Module ...................................................... 187 Oscillator Start-up Timer ........................................... 182 Output Compare Module........................................... 186 Power-up Timer ........................................................ 182 Reset......................................................................... 182 SPI Module Master Mode (CKE = 0) .................................... 191 Master Mode (CKE = 1).................................... 192 Slave Mode (CKE = 0)...................................... 193 Slave Mode (CKE = 1)...................................... 194 Type A, B and C Timer External Clock ..................... 184 Watchdog Timer ....................................................... 182 Timing Diagrams CAN Bit..................................................................... 110 Frame Sync, AC-Link Start of Frame ....................... 120 Frame Sync, Multi-Channel Mode ............................ 120 I2S Interface Frame Sync ......................................... 120 PWM Output ............................................................... 83 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ..................... 142 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ..................... 142 Time-out Sequence on Power-up (MCLR Tied to VDD) ......................................... 142 Timing Diagrams and Specifications DC Characteristics - Internal RC Accuracy .............. 180 Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion Low-speed ........................................................ 204 Bandgap Start-up Time ............................................ 183 Brown-out Reset....................................................... 183 CAN Module I/O ....................................................... 200 CLKOUT and I/O ...................................................... 181 DCI Module AC-Link Mode................................................... 190 Multichannel, I2S Modes................................... 189 External Clock .......................................................... 179 I2C Bus Data (Master Mode) .................................... 197 I2C Bus Data (Slave Mode) ...................................... 199 Input Capture............................................................ 186 Oscillator Start-up Timer........................................... 183 Output Compare Module .......................................... 186 Power-up Timer ........................................................ 183 Reset ........................................................................ 183 Simple OC/PWM Mode ............................................ 187 SPI Module Master Mode (CKE = 0).................................... 191 Master Mode (CKE = 1).................................... 192 Slave Mode (CKE = 0)...................................... 193 Slave Mode (CKE = 1)...................................... 195 Type A Timer External Clock .................................... 184 Type B Timer External Clock .................................... 185 Type C Timer External Clock.................................... 185 Watchdog Timer ....................................................... 183 Timing Specifications PLL Clock ................................................................. 180 Trap Vectors ....................................................................... 42 U UART Module Address Detect Mode ............................................... 101 Auto Baud Support ................................................... 102 Baud Rate Generator ............................................... 101 Enabling and Setting Up ............................................. 99 Framing Error (FERR) .............................................. 101 Idle Status................................................................. 101 Loopback Mode ........................................................ 101 Operation During CPU Sleep and Idle Modes.......... 102 Overview..................................................................... 97 Parity Error (PERR) .................................................. 101 Receive Break .......................................................... 101 Receive Buffer (UxRXB)........................................... 100 |
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