DML1010FDK

Document number: DS40878 Rev. 3 - 2

9 of 11

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June 2022

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DML1010FDK

Application Information (continued)

Thermal Considerations

To ensure proper operation, the maximum junction temperature of the DML1010FDK should not exceed +150°C. Several factors attribute to the

junction temperate rise: load current, MOSFET on-resistance, junction-to-ambient thermal resistance, and ambient temperature. The maximum

load current can be determined by:

Where



ILOAD(MAX) is the maximum allowable current on load (A). (6A for DML1010FDK)



TJ(MAX) is the maximum allowable junction temperature.



TC is the case temperature of the device.



θJC = Junction to case thermal impedance. This parameter is highly dependent upon PCB layout.

PCB Layout Consideration

1.

Place the input/output capacitors CIN and COUT as close as possible to the IN and OUT pins.

2.

The power traces which are IN trace, OUT trace, and GND trace should be short, wide, and direct for minimizing parasitic inductance.

3.

Place CVBIAS capacitor near the device pin.

4.

Connect the signal ground to the GND pin, and keep a single connection from GND pin to the power ground behind the input or output

capacitors.

5.

For better power dissipation, via holes are recommended to connect the exposed pad’s landing area to a large copper polygon on the other

side of the printed circuit board. The copper polygons and exposed pad shall connect to IN pin on the printed circuit board.

PGND (Power)

CIN

COUT

CVBIAS

VOUT

VIN

GND (Signal)

2

1

3

4

7

8

6

5

IN

VBIAS

ON

OUT

GND

IN

IN

EPAD

OUT

OUT