SLG47502V datasheet(4/192 Pages) RENESAS

4 / 192 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

4 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Figures

Figure 1: Block Diagram............................................................................................................................................................. 7

Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................26

Figure 3: GPI Structure Diagram..............................................................................................................................................28

Figure 4: GPIO with I2C Mode IO Structure Diagram...............................................................................................................29

Figure 5: Matrix OE IO Structure Diagram ...............................................................................................................................30

Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C .......................................................31

Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ......................31

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .........................................32

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ......................32

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................33

Figure 11: Connection Matrix ...................................................................................................................................................34

Figure 12: Connection Matrix Usage Example.........................................................................................................................34

Figure 13: 2-bit LUT0 or DFF0 or Shift Register0 ....................................................................................................................42

Figure 14: 2-bit LUT1 or DFF1 or Shift Register1 ....................................................................................................................42

Figure 15: 2-bit LUT2 or DFF2 or Shift Register2 ....................................................................................................................43

Figure 16: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation ............................................................................43

Figure 17: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with DFF Initial Value = 1 ...................................44

Figure 18: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with Initial Value = b0001 ...................................45

Figure 19: 2-bit LUT3 or PGen .................................................................................................................................................47

Figure 20: PGen Timing Diagram.............................................................................................................................................47

Figure 21: 3-bit LUT0 or DFF3 or Shift Register 3 ...................................................................................................................49

Figure 22: 3-bit LUT1 or DFF4 or Shift Register 4 ...................................................................................................................50

Figure 23: 3-bit LUT2 or DFF5 or Shift Register 5 ...................................................................................................................50

Figure 24: 3-bit LUT3 or DFF6 or Shift Register 6 ...................................................................................................................51

Figure 25: 3-bit LUT4 or DFF7 or Shift Register 7 ...................................................................................................................51

Figure 26: 3-bit LUT5 or DFF8 or Shift Register 8 ...................................................................................................................52

Figure 27: 3-bit LUT6 or DFF9 or Shift Register 9 ...................................................................................................................52

Figure 28: 3-bit LUT7 or DFF10 or Shift Register 10 ...............................................................................................................53

Figure 29: 3-bit LUT8 or DFF11 or Shift Register 11 ...............................................................................................................53

Figure 30: 3-bit LUT9 or DFF12 or Shift Register 12 ...............................................................................................................54

Figure 31: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation ......................................................................54

Figure 32: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b10011011 ................55

Figure 33: DFF3 to DFF12 and Shift Register3 to Shift Register12 Operation, nReset, Initial Value: b10011011, Case2......55

Figure 34: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nReset, Initial Value: b00011011 ................56

Figure 35: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010 ....................56

Figure 36: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b00011010, Case 2.......57

Figure 37: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation, nSet, Initial Value: b10011010 ....................57

Figure 38: 4-bit LUT0 or DFF13 or Shift Register 13 ...............................................................................................................60

Figure 39: DFF13 and Shift Register 13 Operation..................................................................................................................61

Figure 40: DFF13 and Shift Register 13 Operation, nSet, Initial Value: xA7B2 .......................................................................61

Figure 41: DFF13 and Shift Register 13 Operation, nReset, Initial Value: xA7B2 ...................................................................62

Figure 42: Possible Connections Inside Multi-Function Macrocell ...........................................................................................64

Figure 43: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF15, CNT/DLY1) .................................................65

Figure 44: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF16, CNT/DLY2) .................................................66

Figure 45: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF17, CNT/DLY3) .................................................67

Figure 46: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF18, CNT/DLY4) .................................................68

Figure 47: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF19, CNT/DLY5) .................................................69

Figure 48: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF20, CNT/DLY6) .................................................70

Figure 49: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT16/DFF21, CNT/DLY7) .................................................71

Figure 50: 4-bit LUT1 or CNT/DLY0.........................................................................................................................................74

Figure 51: Delay Macrocell Behavior with Different Oscillators Options (Edge Select: Both, Counter Data: 3).......................76

Figure 52: Delay Mode Timing Diagram (Rising, Falling, and Both Edge Detection)...............................................................77

Figure 53: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................77

Figure 54: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................78

Figure 55: One-Shot Function Timing Diagram........................................................................................................................79

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