SLG47502V datasheet(5/192 Pages) RENESAS

5 / 192 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

5 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Figure 56: Frequency Detection Mode Timing Diagram...........................................................................................................80

Figure 57: Edge Detection Mode Timing Diagram ...................................................................................................................81

Figure 58: Delayed Edge Detection Mode Timing Diagram .....................................................................................................82

Figure 59: Counter Value, Counter Data = 3............................................................................................................................83

Figure 60: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP=0) for CNT Data = 3..........83

Figure 61: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 0) for CNT Data = 3............84

Figure 62: CNT/FSM Mode Timing Diagram (Reset Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3........84

Figure 63: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, OSC is Forced On, UP = 1) for CNT Data = 3............85

Figure 64: DLY/FSM Mode, Falling Edge Delay, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 ....................85

Figure 65: One Shot/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 .......................85

Figure 66: Freq. Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 ...............86

Figure 67: Delayed Edge Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 .86

Figure 68: Wake/Sleep Controller ............................................................................................................................................87

Figure 69: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ..........................................................88

Figure 70: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used .............................................................88

Figure 71: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ..............................................................89

Figure 72: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used .................................................................89

Figure 73: ACMP0H Block Diagram.........................................................................................................................................92

Figure 74: ACMP1H Block Diagram.........................................................................................................................................93

Figure 75: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Hysteresis = 0, VDD = 1.0 V to 1.65 V...94

Figure 76: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, VDD = 1.0 V to 1.65 V ...........................................94

Figure 77: Programmable Delay ..............................................................................................................................................95

Figure 78: Edge Detector Output .............................................................................................................................................95

Figure 79: Deglitch Filter/Edge Detector Simplified Structure ..................................................................................................96

Figure 80: Voltage Reference Block Diagram ..........................................................................................................................98

Figure 81: Typical Load Regulation, Vref = 200 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................99

Figure 82: Typical Load Regulation, Vref = 400 mV, T = -40 °C to +85 °C, Buffer - Enable....................................................99

Figure 83: Typical Load Regulation, Vref = 600 mV, T = -40 °C to +85 °C, Buffer - Enable.................................................. 100

Figure 84: Typical Load Regulation, Vref = 850 mV, T = -40 °C to +85 °C, Buffer - Enable.................................................. 100

Figure 85: Typical Input Offset Voltage vs. Vref at VDD = 1.2 V, T = 25 °C ...........................................................................101

Figure 86: Oscillator0 Block Diagram.....................................................................................................................................103

Figure 87: Oscillator1 Block Diagram.....................................................................................................................................104

Figure 88: Clock Scheme ....................................................................................................................................................... 105

Figure 89: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz................................................................................ 106

Figure 90: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz.................................................................................... 106

Figure 91: Oscillators Total Error vs. Temperature, VDD = 1.0 V to 1.65 V............................................................................107

Figure 92: Oscillator0 Settling Time, VDD = 1.2 V, T = 25 °C, OSC0 = 2.048 kHz.................................................................108

Figure 93: Oscillator1 Settling Time, VDD = 1.2 V, T = 25 °C, OSC1 = 25 MHz (Normal Start).............................................108

Figure 94: Oscillator1 Settling Time, VDD = 1.2 V, T = 25 °C, OSC1 = 25 MHz (Start with Delay)........................................109

Figure 95: POR Sequence ..................................................................................................................................................... 111

Figure 96: Internal Macrocell States During POR Sequence ................................................................................................. 112

Figure 97: Power-Down.......................................................................................................................................................... 113

Figure 98: Basic Command Structure .................................................................................................................................... 115

Figure 99: I2C General Timing Characteristics....................................................................................................................... 115

Figure 100: Byte Write Command, R/W = 0........................................................................................................................... 116

Figure 101: Sequential Write Command ................................................................................................................................ 116

Figure 102: Current Address Read Command, R/W = 1........................................................................................................ 117

Figure 103: Random Read Command ................................................................................................................................... 117

Figure 104: Sequential Read Command ................................................................................................................................ 117

Figure 105: Reset Command Timing .....................................................................................................................................118

Figure 106: Example of I2C Byte Write Bit Masking............................................................................................................... 119

Figure 107: Analog Temperature Sensor Structure Diagram................................................................................................. 122

Figure 108: TS Output vs. Temperature, VDD = 1.0 V to 1.65 V ............................................................................................123

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