SLG47502V datasheet(95/192 Pages) RENESAS

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Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

95 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Programmable Delay/Edge Detector

The SLG47512/13 has a programmable time delay logic cell that can generate a delay that is selectable from one of four timings

configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns, rising

edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further modified

with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay period.

See Figure 77 and Figure 78 for further information.

Note: The input signal must be longer than the delay, otherwise it will be filtered out.

10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT

Please refer to Table 11.

Figure 77: Programmable Delay

Figure 78: Edge Detector Output

Programmable

Delay

OUT

registers [1443:1442]

From Connection Matrix Output [92]

To Connection

Matrix Input [40]

registers [1441:1440]

Edge Mode Selection

Delay Value Selection

time1

Edge Detector

Output

Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

time1

time1 is a fixed value

time2 delay value is selected via register

time2

width

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