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SLG47502V Datasheet(PDF) 17 Page - Renesas Technology Corp

Part # SLG47502V
Description  Low Voltage GreenPAK Programmable Mixed-Signal Matrix
PDF  192 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SLG47502V Datasheet(HTML) 17 Page - Renesas Technology Corp

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Datasheet
28-Feb-2023
CFR0011-120-00
Revision 2.3
17 of 194
© 2023 Renesas Electronics Corporation
SLG47512/13
Low Voltage GreenPAK Programmable
Mixed-Signal Matrix
Preliminary
VOL
LOW-Level Output Voltage
Open-Drain at 2 mA sink current
0
0.2xVDD
V
Open-Drain at 3 mA sink current
0
0.4
V
IOL
LOW-Level Output Current
VDD = 1.3 V, VOL = 0.2 V
3
--
mA
tof
Output Fall Time from VIHmin to
VILmax
--
250
ns
Ii
Input Current each IO Pin
0.1xVDD < VI < 0.9xVDDmax
-10
+10
mA
Ci
Capacitance for each IO Pin
T = 25 °C,
VDD = 1.2 V to 1.7 V
--
10
pF
Table 9: I2C Pins Timing Characteristics for DI Mode, T = -40 °C to +85 °C, Full VDD Range Unless Otherwise Noted
Parameter
Description
Condition
Speed
Unit
400 kHz
1 MHz
Min
Max
Min
Max
FSCL
Clock Frequency, SCL
--
400
--
1000
kHz
tLOW
Clock Pulse Width Low
1300
--
500
--
ns
tHIGH
Clock Pulse Width High
600
--
260
--
ns
tI
Input Filter Spike Suppression
(SCL, SDA)
50
--
50
--
ns
tVD_ACK
Data Valid Acknowledge Time
--
900
--
450
ns
tBUF
Bus Free Time between Stop and
Start
1300
--
500
--
ns
tHD_STA
Start Hold Time
600
--
260
--
ns
tSU_STA
Start Set-up Time
600
--
260
--
ns
tHD_DAT
Data Hold Time (Note 1)
55
--
55
--
ns
tSU_DAT
Data Set-up Time
100
--
50
--
ns
tR
Inputs Rise Time
--
300
--
120
ns
tF
Inputs Fall Time
--
300
--
120
ns
tSU_STO
Stop Set-up Time
600
--
260
--
ns
tVD_DAT
Data Valid Time
--
900
--
450
ns
Note 1 Does not meet standard I2C specifications: tHD_DAT = 0 ns (min) for Fast-Mode and Fast-Mode Plus.
Note 2 Timing diagram can be found in Figure 99.
Table 10: I2C Pins Timing Characteristics for DILV Mode, T = -40 °C to +85 °C, Full VDD Range Unless Otherwise Noted
Parameter
Description
Condition
Speed
Unit
400 kHz
Min
Max
FSCL
Clock Frequency, SCL
--
400
kHz
tLOW
Clock Pulse Width Low
1300
--
ns
tHIGH
Clock Pulse Width High
600
--
ns
tI
Input Filter Spike Suppression (SCL,
SDA)
50
--
ns
Table 8: EC of the I2C Pins for DILV Mode at T = -40 °C to +85 °C, Full VDD Range Unless Otherwise Noted (Continued)
Parameter
Description
Condition
Fast-Mode
Unit
Min
Max



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