MC68340 datasheet(175/441 Pages) FREESCALE

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MC68340 USER’S MANUAL

MOTOROLA

All exception processing is performed at the supervisor level. All bus cycles generated

during exception processing are supervisor references, and all stack accesses use the

SSP.

Instructions that have important system effects can only be executed at supervisor level.

For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET

instructions. To prevent a user program from gaining privileged access, except in a

controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP

#n instruction provides controlled user access to operating system services.

5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor

executes instructions at the user privilege level. The bus cycles for an instruction executed

at the user privilege level are classified as user references, and the values of the function

codes on FC2–FC0 specify user address spaces. While the processor is at the user level,

implicit references to the system SP and explicit references to address register seven (A7)

refer to the USP.

5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to

supervisor privilege level, a condition that causes exception processing must occur. When

exception processing begins, the current values in the SR, including the S-bit, are saved

on the supervisor stack, and then the S-bit is set to enable supervisory access. Execution

continues at supervisor privilege level until exception processing is complete.

To return to user access level, a system routine must execute one of the following

instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These

instructions execute only at supervisor privilege level and can modify the S-bit of the SR.

After these instructions execute, the instruction pipeline is flushed, then refilled from the

appropriate address space.

The RTE instruction causes a return to a program that was executing when an exception

occurred. When RTE is executed, the exception stack frame saved on the supervisor

stack can be restored in either of two ways.

If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the

SR and PC are restored to the values saved on the supervisor stack, and execution

resumes at the restored PC address, with access level determined by the S-bit of the

restored SR.

If the frame was generated by a bus error or an address error exception, the entire

processor state is restored from the stack.

5.5 EXCEPTION PROCESSING

An exception is a special condition that preempts normal processing. Exception

processing is the transition from normal mode program execution to execution of a routine

that deals with an exception. The following paragraphs discuss system resources related

to exception handling, exception processing sequence, and specific features of individual

exception processing routines.

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