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MC68340 Datasheet(PDF) 178 Page - Freescale Semiconductor, Inc

Part # MC68340
Description  Integrated Processor with DMA User?셲 Manual
PDF  441 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 178 Page - Freescale Semiconductor, Inc

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MOTOROLA
MC68340 USER’S MANUAL
5- 41
Finally, the processor prepares to resume normal execution of instructions. The exception
vector offset is determined by multiplying the vector number by 4, and the offset is added
to the contents of the VBR to determine displacement into the exception vector table. The
exception vector is loaded into the PC. If no other exception is pending, the processor will
resume normal execution at the new address in the PC.
5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile
portion of the current context is saved on the top of the supervisor stack. This context is
organized in a format called the exception stack frame.
The exception stack frame always includes the contents of SR and PC at the time the
exception occurred. To support generic handlers, the processor also places the vector
offset in the exception stack frame and marks the frame with a format code. The format
field allows an RTE instruction to identify stack information so that it can be properly
restored.
The general form of the exception stack frame is illustrated in Figure 5-10. Although some
formats are peculiar to a particular M68000 Family processor, format 0000 is always legal
and always indicates that only the first four words of a frame are present. See 5.5.4
CPU32 Stack Frames for a complete discussion of exception stack frames.
STATUS REGISTER
PROGRAM COUNTER LOW
FORMAT
VECTOR OFFSET
OTHER PROCESSOR STATE INFORMATION,
DEPENDING ON EXCEPTION
(0, 2, OR 8 WORDS)
PROGRAM COUNTER HIGH
SP
15
0
Figure 5-10. Exception Stack Frame
5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on
its relative importance to system operation. Priority assignments are shown in Table 5-17.
Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest
priorities. Exception processing for exceptions that occur simultaneously is done by
priority, from highest to lowest.
It is important to be aware of the difference between exception processing mode and
execution of an exception handler. Each exception has an assigned vector that points to
an associated handler routine. Exception processing includes steps described in 5.5.1.2
Exception Processing Sequence, but does not include execution of handler routines,
which is done in normal mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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