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LPC804 Datasheet(PDF) 22 Page - NXP Semiconductors

Part # LPC804
Description  32-bit Arm® Cortex®-M0 microcontroller; up to 32 KB flash and 4 KB SRAM; 12-bit ADC; Comparator; 10-bit DAC; Capacitive Touch Interface; Programmable Logic Unit
PDF  89 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC804 Datasheet(HTML) 22 Page - NXP Semiconductors

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LPC804
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2023. All rights reserved.
Product data sheet
Rev. 2.1 — 25 July 2023
22 of 87
NXP Semiconductors
LPC804
32-bit Arm Cortex-M0+ microcontroller
9.13.1 Features
• Maximum data rates of up to 15 Mbit/s in master mode and up to 20 Mbit/s in slave
mode for SPI functions connected to all digital pins.
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data, which can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data, which allows very
versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
9.14 I2C-bus interface (I2C0 and I2C1)
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master.
9.14.1 Features
• I2C0 and I2C1 support standard and fast mode with data rates of up to 400 kbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
9.15 Capacitive Touch Interface
The Capacitive Touch interface is designed to handle up to five capacitive buttons in
different sensor configurations, such as slider, and button matrix. It operates in sleep,
deep sleep, and power-down modes, allowing very low power performance.
The Capacitive Touch module measures the change in capacitance of an electrode plate
when an earth-ground connected object (for example, finger) is brought within close
proximity.
9.16 CTimer
9.16.1 General-purpose 32-bit timers/external event counter
The LPC804 has one general-purpose 32-bit timer/counter.



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