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LPC804 Datasheet(PDF) 36 Page - NXP Semiconductors |
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LPC804 Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 89 page ![]() LPC804 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 25 July 2023 36 of 87 NXP Semiconductors LPC804 32-bit Arm Cortex-M0+ microcontroller A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 9.26.2 Brownout detection The LPC804 includes one reset level and three interrupt levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. One threshold level can be selected to cause a forced reset of the chip. Fig 16. Reset pad configuration VSS reset aaa-004613 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN |
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