MCP3910 datasheet(22/90 Pages) MICROCHIP

22 / 90 page

MCP3910

DS20005116D-page 22

 2012-2020 Microchip Technology Inc.

3.13

Chip Select/ Boost Logic Input

(CS/BOOST)

In SPI mode, this pin is the SPI Chip Select that

enables serial communication. When this pin is logic

high, no communication can take place. A chip select

falling edge initiates serial communication and a chip

select rising edge terminates the communication. No

communication can take place, even when CS is logic

low, if RESET is also logic low.

This input is Schmitt triggered.

In Two-Wire Interface mode, this is the Boost Logic

Select Input pin (see Section 7.0 “Two-Wire Serial

Interface Description”

for the logic input table for

BOOST). The pin state is latched when the mode

changes to Two-Wire Interface mode and is relatched

at each Watchdog Timer Reset.

3.14

Serial Data Clock/

Master Clock Input (SCK/MCLK)

In SPI mode, this is the Serial Clock pin for SPI

communication. Data are clocked into the device on the

rising edge of SCK. Data are clocked out of the device

on the falling edge of SCK.

The MCP3910 SPI interface is compatible with SPI 0,0

and 1,1 modes. SPI modes can be changed during a

CS high time.

The maximum clock speed specified is 20 MHz. SCK

and MCLK are two different and asynchronous clocks;

SCK is only required when a communication happens,

while MCLK is continuously required when the part is

converting analog inputs.

This input is Schmitt triggered.

In the Two-Wire Interface mode, this pin is defining the

Master Clock of the device (MCLK) and simultane-

ously, as the Serial Clock (SCK) for the interface. In this

mode, the clock has to be provided continuously to

ensure proper operation. See Section 7.0 “Two-Wire

Serial Interface Description”

for more information

and timing diagrams of the Two-Wire Interface mode

protocol.

3.15

Serial Data Output (SDO)

This is the SPI Data Output pin. Data are clocked out of

the device on the falling edge of SCK.

This pin remains in a high-impedance state during the

command byte. It also stays high-impedance during the

entire communication for WRITE commands and when

the CS pin is logic high, or when the RESET pin is logic

low. This pin is active only when a READ command is

processed. The interface is half duplex (inputs and

outputs do not happen at the same time).

In the Two-Wire Interface mode, this pin is the only

digital output pin and sends synchronous frames at

each data ready event with data bits clocked out on the

falling edge of SCK.

3.16

Serial Data/OSR1 Logic Input

(SDI/OSR1)

This is the SPI Data Input pin. Data are clocked into the

device on the rising edge of SCK. When CS is logic low,

this pin is used to communicate with a series of 8-bit

commands. The interface is half duplex (inputs and

outputs do not happen at the same time).

Each communication starts with a chip select falling

edge, followed by an 8-bit command word, entered

through the SDI pin. Each command is either a READ or

a WRITE command. Toggling SDI after a READ or a

WRITE

command, when CS is logic high, has no effect.

This input is Schmitt triggered.

In Two-Wire Interface mode, this is the OSR1 Logic

Select Input pin (see Section 7.0 “Two-Wire Serial

Interface Description”

for the logic input table for

OSR0 and OSR1). The pin state is latched when the

mode changes to Two-Wire Interface mode and is

relatched at each Watchdog Timer Reset.

3.17

Exposed Pad (EP)

This pin is the Exposed Thermal Pad. It must be

connected to AGND for optimal accuracy and thermal

performance. This pad can also be left floating if neces-

sary. Connecting it to AGND is preferable for the lowest

noise performance and best thermal behavior.

MCP3910 Datasheet(PDF) 22 Page - Microchip Technology

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