MCP3910 datasheet(57/90 Pages) MICROCHIP

57 / 90 page

 2012-2020 Microchip Technology Inc.

DS20005116D-page 57

MCP3910

FIGURE 7-2:

Frame Word.

These four frames can be used to multiplex SDO at the

output of the digital isolators. In this case, up to four

channels (typically three phases and one neutral for

energy metering applications) can be multiplexed. The

output data of each individual MCP3910 device can be

attributed to a different frame (FRAME0, 1, 2 or 3) and

retrieved on a single SDO line after the digital isolators,

provided that the isolators have a chip enable or a multi-

plexing feature. The frame counter can then be used to

retrieve the information about which MCP3910 part is

actually being read. After the four frames have been

transmitted, the SDO pin Idles logic low to reduce digital

isolator power consumption until the next data are avail-

able. If OSR = 64, the SDO never Idles because the data

are directly available after the four frames are transmit-

ted. Figure 7-3 displays the timing diagram for Two-Wire

Interface mode, showing all OSR possibilities. Note that

the first set of frames is sent only when the first data are

ready, which means that the settling time of the SINC

filter will be elapsed before sending the first set of

frames, as represented in Figure 7-3.

It should also be noted that since the PHASE register

is back to its default value in the Two-Wire mode, there

is no delay between the two channels in this mode and

the conversions start after a delay of OSR/2 DMCLK

periods (which corresponds to 2 x OSR MCLK

periods).

FIGURE 7-3:

MCP3910 Two-Wire Communication Protocol.

CRCCOM<15:0>

DATA_CH0<23:0>

DATA_CH1<23:0>

SYNC WORD (2 Bytes)

SDO OUTPUT FRAME (10 Bytes, 80x clocks per Frame)

CHANNEL 0 ADC DATA (3 Bytes)

CHANNEL 1 ADC DATA (3 Bytes)

SDO

SCK/

MCLK

CRCCOM<15:0>

CRCCOM on Entire Frame (2 Bytes)

DATA_CH0<15:0>

DATA_CH1<15:0>

SYNC WORD (2 Bytes)

SDO OUTPUT FRAME (8 Bytes, 64x clocks per Frame)

CHANNEL 0 ADC DATA (2 Bytes)

CHANNEL 1 ADC DATA (2 Bytes)

SDO

SCK/

MCLK

FRAME CLOCKING FOR OSR>64

FRAME CLOCKING FOR OSR=64

CRCCOM on Entire Frame (2 Bytes)

TABLE 7-4:

FRAME COUNTER SETTINGS

CNT1

CNT0

FRAME NUMBER

FRAME0

FRAME1

FRAME2

FRAME3

SDO

(OSR=64)

OSC2/

MODE

SCK/MCLK

2-Wire Mode

(2*OSR)x

clocks

Hi-Z

SDO

(OSR=128)

SDO

(OSR=256)

SDO

(OSR=512)

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

DATA=D1

DATA=D2

DATA=D3

DATA=D4

DATA=D5

DATA=D6

DATA=D7

DATA=D8

DATA=D9

DATA=D10 DATA=D11 DATA=D12 DATA=D13 DATA=D14 DATA=D15 DATA=D16 DATA=D17 DATA=D18 DATA=D19 DATA=D20 DATA=D21 DATA=D22 DATA=D23 DATA=D24

Internal data ready (Data is unsettled). No

frame is transmitted

Data Ready.

New data is available

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

256x

clocks

DATA=D25 DATA=D26 DATA=D27 DATA=D28 DATA=D29

-OSR/2

256x

clocks

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