MCP3910 datasheet(38/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 38

 2012-2020 Microchip Technology Inc.

5.6

Voltage Reference

5.6.1

INTERNAL VOLTAGE REFERENCE

The MCP3910 contains an internal voltage reference

source specially designed to minimize drift over

temperature. In order to enable the internal voltage

reference, the VREFEXT bit in the CONFIG1 register

must be set to ‘0’ (default mode). This internal VREF

supplies reference voltage to all channels. The typical

value of this voltage reference is 1.2V, ±2%. The

internal reference has a very low typical temperature

coefficient of ±9 ppm/°C, allowing the output to have

minimal variation with respect to temperature, since it

is proportional to (1/VREF).

The noise of the internal voltage reference is low

enough not to significantly degrade the SNR of the

ADC if compared to a precision external low noise

voltage reference. The output pin for the internal

voltage reference is REFIN+/OUT.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna

created by the REFIN+/OUT pin, if left floating.

The bypass capacitors also help in applications where

the voltage reference output is connected to other

circuits. In this case, additional buffering may be

needed, since the output drive capability of this output

is low.

Adding too much capacitance on the REFIN+/OUT pin

may slightly degrade the THD performance of the

ADCs.

5.6.2

DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS

When the VREFEXT bit is set to ‘1’, the two reference

pins (REFIN+/OUT, REFIN-) become a differential volt-

age reference input. The voltage at the REFIN+/OUT is

noted VREF+ and the voltage at the REFIN- pin is noted

VREF-. The differential voltage input value is given by

Equation 5-4.

EQUATION 5-4:

The specified VREF range is from 1.1V to 1.3V. The

REFIN- pin voltage (VREF-) should be limited to ±0.1V,

with respect to AGND. Typically, for single-ended refer-

ence applications, the REFIN- pin should be directly

connected to AGND with its own separate track to avoid

any spike due to switching noise.

5.6.3

TEMPERATURE COMPENSATION

(VREFCAL[7:0])

The internal voltage reference consists of a proprietary

circuit and algorithm to compensate first-order and

second-order temperature coefficients. The compensa-

tion enables very low-temperature coefficients (typically,

9 ppm/°C) on the entire range of temperatures, from

-40°C to +125°C. This temperature coefficient varies

from part to part.

This temperature coefficient can be adjusted on each

part through the VREFCAL[7:0] bits present in the

CONFIG0 register (bits 7 to 0). These register settings

are only for advanced users. VREFCAL[7:0] should not

be modified unless the user wants to calibrate the

temperature coefficient of the whole system or applica-

tion. The default value of this register is set to 0x50. This

value was chosen to optimize the standard deviation of

the tempco across process variation. The value can be

slightly improved to around 7 ppm/°C if the VREFCAL[7:0]

are written at 0x42, but this setting degrades the standard

deviation of the VREF tempco. The typical variation of the

temperature coefficient of the internal voltage reference,

with respect to the VREFCAL register code, is given by

Figure 5-7. Modifying the

value

stored

in the

VREFCAL[7:0] bits may also vary the voltage reference,

in addition to the temperature coefficient.

FIGURE 5-7:

VREF Tempco vs.

VREFCAL[7:0] Trim Code Chart.

5.6.4

VOLTAGE REFERENCE BUFFERS

Each channel includes a voltage reference buffer tied

to the REFIN+/OUT pin, which allows the device to

properly charge the internal capacitors with the voltage

reference signals, even in the case of an external

voltage reference connection with weak load regulation

specifications. This ensures that the correct amount of

current is sourced to each channel to ensure their

accuracy specifications, and diminishes the constraints

on the voltage reference load regulation.

VREF =VREF+– VREF-

128

192

256

VREFCAL Register Trim Code (decimal)

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