MCP3910 datasheet(42/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 42

 2012-2020 Microchip Technology Inc.

5.11

Data Ready Status Bits

In addition to the Data Ready pin indicator, the

MCP3910 device includes a separate data ready status

bit for each channel. Each ADC channel, CHn, is

associated with the corresponding DRSTATUS[n] that

can be read at all times in the STATUSCOM register.

These status bits can be used to synchronize the data

retrieval in case the DR pin is not connected (see

Section 6.8

“ADC

Channels

Latching

and

Synchronization”

The DRSTATUS[1:0] bits are not writable; writing on

them has no effect. They have a default value of ‘1’,

which indicates that the data of the corresponding ADC

are not ready. This means that the ADC Output register

has not been updated since the last reading (or since

the last Reset). The DRSTATUS bits take the ‘0’ state

once the ADC Channel register is updated (which

happens at a DRCLK rate). A simple read of the

STATUSCOM register clears all the DRSTATUS bits to

their default value (‘1’).

In the case of DR_LINK = 1, the DRSTATUS[1:0] bits

are all updated synchronously with the most lagging

channel; in the same time, the data ready pulse is

generated. In case of DR_LINK = 0, each DRSTATUS

bit is updated independently and synchronously with its

corresponding channel.

5.12

Data Ready Link

There are two modes defined with the DR_LINK bit, in

the STATUSCOM register, that control the data ready

pulses. The position of the data ready pulses varies

with respect to this mode, to the OSR[2:0] and to the

PHASE register settings. Figure 5-9 represents the

behavior of the Data Ready pin with the two DR_LINK

configurations.

• DR_LINK = 0: Both data ready pulses from ADC

Channel 0 and ADC Channel 1 are output on the

DR pin.

• DR_LINK = 1 (Recommended and Default mode):

Only the data ready pulses from the most lagging

ADC, between all the active ADCs, are present on

the DR pin.

The lagging ADC data ready position depends on the

PHASE0/1 registers, the PRE[1:0] and the OSR[2:0]

settings. In this mode, the active ADCs are linked

together, so their data are latched together when the

lagging ADC output is ready. For power metering appli-

cations, DR_LINK = 1 is recommended (default mode).

It allows the host MCU to gather all channels synchro-

nously within a unique interrupt pulse and it ensures

that all channels have been latched at the same time,

so that no data corruption is happening.

FIGURE 5-9:

DR_LINK Configurations.

One DRCLK period

(OSR times DMCLK periods)

DR_LINK =

Only the most lagging data ready is present

All channels are latched together at DR falling edge

DR_LINK =

All channels data ready

are present

Data ready pulse

from CH1

Data ready pulse from

CH1 channel (reference)

PHASE =

PHASE <

PHASE >

Data ready pulse from

most lagging ADC channel

(here CH0 channel lags)

Data ready pulse from

most lagging ADC channel

Data ready pulse from CH0

channel if PHASE <

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