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UPD16331 Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # UPD16331
Description  MOS INTEGRATED CIRCUIT
PDF  18 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD16331 Datasheet(HTML) 6 Page - Renesas Technology Corp

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µPD16331
PIN DESCRIPTION
Pin Symbol
Pin Name
Pin No.
Description
PC
Inverted polarity input
27
PC = H: Polarity of all outputs inverted
BLK
Blanking input
37
BLK = H: All outputs = H or L
STB
Latch strobe input
36
L: Through
H: Data retained
ANote
RIGHT data input
30
When R/L = H, A: Input B: Output
BNote
LEFT data input
35
When R/L = L, A: Output B: Input
CLK
Clock input
31
Shift executed on rise
CLR
Clear input
32
L: All shift registers set to “L”
R/L
Shift control input
25
H: Right shift mode
A
→ O1 . . . O40 → B
L: Left shift mode
B
→ O40 . . . O1 → A
O1 to O40
High breakdown voltage output
1 to 20, 45 to 64
100 V, 150 mA MAX.
VDD1
Logic block power supply
26, 39
5 V
± 10 %
VDD2
Driver block power supply
21, 44, 65, 66, 79, 80
30 to 90 V
VSS1
Logic ground
24, 41,
Connected to system GND
VSS2
Driver ground
22, 23, 42, 43, 67 to 78
Connected to system GND
NC
Non-connection pins
28, 29, 33, 34, 38, 40
Non-connection
Note
Data which is input to the shift registers is always inverted input data A (B) and data in the shift registers is
always inverted when it is output. (Refer to the truth tables and timing chart.)
TRUTH TABLE 1 (Shift Register Block)
Input
Output
Shift Register
R/L
CLK
A
B
H
↑
Input
OutputNotes 1
Right shift executed
H
H or L
Output
Retained
L
↑
OutputNotes 2
Input
Left shift executed
L
H or L
Output
Retained
Notes 1. The data of internal shift register S39 is shifted to S40 on a rise of CLK and inverted data of S40 is output from
B. (Refer to the timing chart.)
2. The data of internal shift register S2 is shifted to S1 on a rise of CLK and inverted data of S1 is output from
A. (Refer to the timing chart.)
TRUTH TABLE 2 (Latch Block)
STB
Operation
H
Retains data immediately before STB becomes H.
L
Outputs data of shift register.
TRUTH TABLE 3 (Driver Block)
Input
State of Driver Output
A (B)
STB
BLK
PC
××
H
H
L (all driver outputs: L)
××
H
L
H (all driver outputs: H)
LL
L
H
H
LL
LL
L
HL
LH
L
HL
L
L
H
×
H
L
H
Outputs data of Sn on STB rise.
×
H
L
L
Inverts and outputs data of Sn on STB rise.
×: H or L, H: High level L: Low level



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