7

µPD16331

SWITCHING CHARACTERISTICS (TA = 25

°C, VDD1 = 5.0 V, VDD2 = 90 V, Logic CL = 15 pF, Driver CL = 150 pF)

Item

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Transmission delay time

tPHL1

CLK

→ A/B

50

ns

tPLH1

50

ns

tPLH2

CLR

→ A/B

60

ns

tPHL3

CLK

→ O1 to O40

200

ns

tPLH3

200

ns

tPHL4

STB

→ O1 to O40

180

ns

tPLH4

180

ns

tPHL5

BLK

→ O1 to O40

175

ns

tPLH5

175

ns

tPHL6

PC

→ O1 to O40

170

ns

tPLH6

170

ns

Rise time O1 to O40

tTLH

CL = 150 pF

150

ns

Fall time O1 to O40

tTHL

CL = 150 pF

150

ns

Maximum clock frequency

fmax.

Data fetch, duty = 50%

20

MHz

With cascading, duty = 50%

16

MHz

Input capacitance

CI

15

pF

TIMING REQUIREMENTS (TA =

−20 to +85 °C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V)

Item

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock pulse width

PWCLK

25

ns

Strobe pulse width

PWSTB

60

ns

Blank pulse width

PWBLK

400

ns

Inverted polarity pulse width

PWPC

400

ns

Clear pulse width

PWCLR

120

ns

Data setup time

tsetup

10

ns

Data hold time

thold

10

ns

Clock-strobe time

tCLK-STB

CLK

↑ → STB ↑

60

ns