UPD703003A datasheet(23/45 Pages) RENESAS

23 / 45 page

µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)

Data Sheet U13188EJ6V1DS

(1) Clock timing

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

X1 input cycle

<1>

tCYX

Direct mode

Note 1

PLL mode (PLL locked)

151

Note 2

Note 3

X1 input high-level width

<2>

tWXH

Direct mode

PLL mode

X1 input low-level width

<3>

tWXL

Direct mode

PLL mode

X1 input rise time

<4>

tXR

Direct mode

PLL mode

X1 input fall time

<5>

tXF

Direct mode

PLL mode

CPU operating frequency

—

Note 4

MHz

CLKOUT output cycle

<6>

tCYK

Note 5

CLKOUT input high-level width

<7>

tWKH

0.5T – 5

CLKOUT input low-level width

<8>

tWKL

0.5T – 5

CLKOUT input rise time

<9>

tKR

5ns

CLKOUT input fall time

<10> tKF

5ns

Delay time from X1

↓ to CLKOUT <11> tDXK

Direct mode

Notes 1. When using A/D converter: 100 ns

When not using A/D converter: 250 ns

2. When using A/D converter: The value when

φ = 5 × fXX and φ = fXX are set. Setting φ = 1/2 × fXX is

prohibited.

When not using A/D converter: The value when

φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set.

3. When using A/D converter: 250 ns (when

φ = 5 × fXX is set) and 200 ns (when φ = fXX is set). Setting

φ = 1/2 × fXX is prohibited.

When not using A/D converter: 250 ns (when

φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set).

4. When using A/D converter: 5 MHz

When not using A/D converter: 2 MHz

5. When using A/D converter: 200 ns

When not using A/D converter: 500 ns

Remark

T = tCYK

X1 (input)

CLKOUT (output)

<1>

<2>

<4>

<5>

<6>

<7>

<11>

<8>

<9>

<10>

<3>

UPD703003A Datasheet(PDF) 23 Page - Renesas Technology Corp

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