MP86936

– INTELLI-PHASETM WITH INTEGRATED DRIVER AND MOSFETS

MP86936 Rev. 1.1

www.MonolithicPower.com

11

8/4/2023

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation. For optimal performance, refer to

Figure 3 and follow the guidelines below:

1. Place the input MLCC capacitors as close to

the VIN and PGND pins as possible. Place

the major MLCC capacitors on the same

layer as the MP86936.

2. Place

as

many

VIN

and

PGND

vias

underneath the package as possible, in

between VIN or PGND long pads.

3. Place a VIN copper plane on the second

inner layer to form the PCB stacking (+/-/+)

to reduce parasitic impedance from the input

MLCC capacitor to the MP86936. The

copper plane on the inner layer must cover

the VIN vias underneath the package and the

input MLCC capacitors.

4. Place more PGND vias close to PGND pin

and pad to minimize parasitic resistance and

thermal resistance.

5. Place

the

BST

capacitor

and

VDRV

capacitor

as close to the device’s pins as

possible. Use a ≥20mils trace width to route

the path. Avoid the via for the BST driving

path.

The

bootstrap

capacitor

is

recommended to be 0.1µF to 0.22µF.

6. Place the VDD decoupling capacitor close to

the MP86936. Connect AGND and PGND at

the point of the VDD capacitor

’s ground

connection.

7. Keep the CS signal trace away from high

current paths, such as SW and PWM.

V IN

PG N D

SW

PG N D

SW

SW

SW

V IN

1

2

3

4

5

6

7

8

9

10

11

12

15

14

13

23

22

21

20

19

18

17

16

V IN

Figure 3: Recommended PCB Layout (Placement and Top Layer PCB)

Input capacitor: 0805 package (top side and bottom side), 0402 package (top side)

Inductor: 11nnx8nn package

VDD/BST/VDRV capacitor: 0402 package

Via size: 20/10 ils