MIC2593 datasheet(11/26 Pages) STMICROELECTRONICS

11 / 26 page

April 2004

M9999-042204

MIC2593

Micrel

MIC2593

/INT

SDA

SCL

VSTBY

100k

Disabling SMI when

HPI Control is used

Disabling HPI when

SMI Control is used

100k

/INT

AUXENA

AUXENB

ONA

ONB

MIC2593

Figure 6. Input Pin Configuration for Disabling HPI/SMI Control

Functional Description

Hot Swap Insertion

When circuit boards are inserted into systems carrying live

supply voltages (“hot-plugged”), high inrush currents often

result due to the charging of bulk capacitance that resides

across the circuit board’s supply pins. This transient inrush

current can cause the system’s supply voltages to tempo-

rarily go out of regulation, causing data loss or system

lock-up. In more extreme cases, the transients occurring

during a hot plug event may cause permanent damage to

connectors or on-board components.

The MIC2593 addresses these issues by limiting the inrush

currents to the load (PCI Board), and thereby controlling the

rate at which the load’s circuits turn-on. In addition to this

inrush current control, the MIC2593 offers input and output

voltage supervisory functions and current limiting to provide

robust protection for both the system and circuit board.

System Interface

The MIC2593 employs two system interfaces: the hardware

Hot Plug Interface (HPI) and the System Management Inter-

face (SMI). The HPI includes ON[A/B], AUXEN[A/B], as well

as /FAULT[A/B]; the SMI consists of SDA, SCL, and /INT,

whose signals conform to the levels and timing of the SMBus

specification. The MIC2593 can be operated exclusively from

the SMI, or can employ the HPl for power control while

continuing to use the SMI for access to all but the power

control registers.

In addition to the basic power control features of the MIC2593

accessible by the HPI, the SMI also gives the host access to

the following information from the part:

• Fault conditions occurring on each supply

• GPI[A/B] pin status

When using the System Management Interface for power

control, do not use the Hot Plug Interface. Conversely, when

using the Hot Plug Interface for power control, do not execute

power control commands over the System Management

Interface bus (all other register accesses via the SMI bus

remain permissible while in the HPI control mode). When

utilizing the SMI exclusively, the HPI input pins ON[A/B] and

AUXEN[A/B] should be tied to ground as shown below in

Figure 6 (Disabling HPI when SMI control is used). This

configuration safeguards the power slots in the event that the

SMBus communication link is disconnected for any reason.

Additionally, when utilizing the HPI exclusively, the SMBus

(or SMI) will be inactive if the input pins (SDA, SCL, A0, A1,

and A2) are configured as shown in Figure 6 below (disabling

SMI when HPI Control is used).

Power-On Reset and Power Cycling

The MIC2593 utilizes VSTBY[A/B] as the main supply input

source. VTSBY[A/B] is required for proper operation of the

MIC2593 SMBus interface and registers and must be applied

at all times. A Power-On Reset (POR) cycle is initiated after

VSTBY[A/B] rises above its UVLO threshold and remains

valid at that voltage for 500

µs. All internal registers are

cleared after POR. If VSTBY[A/B] is recycled, the MIC2593

enters a new power-on reset cycle. VSTBY[A/B] must be the

first supply input applied followed by the MAIN supply inputs

of 12V

IN, 12MVIN, 5VIN, and 3VIN. The MAIN supply inputs

may be applied in any order. The SMBus is ready for access

at the end of the POR interval (500

µs after VSTBY[A/B] is

valid). All outputs remain off during t

POR.

Power-Up Cycle

When a slot is off, the 5VGATE and 3VGATE pins are held

low with an internal pull-down current source. When a slot’s

MAIN outputs are enabled by applying a rising-edge signal at

the ON[A/B] control input and all input voltages are above

their respective undervoltage lockout thresholds, all four

main supplies will then execute a controlled turn on. The

5VGATE and 3VGATE pins are each connected to a constant

current source of 25

µA, nominal. Both the 5V and 3.3V

outputs act as source followers, where:

SOURCE = [VGATE – VTH(ON)]

until the associated output is equal to its input. The voltages

on the gates of the external MOSFETs for the 5V and 3.3V

MAIN supplies will continue to rise to approximately 11.5V,

ensuring minimum R

DS(ON) of the MOSFET. Note that a

delay exists between the ON command to a slot and the

appearance of voltage at the slot’s 3.3V or 5V MAIN output.

This delay is the time required to charge the 3V or 5V GATE

output up to the threshold voltage of the external MOSFET

(typically about 4V). For the 5V and 3.3V MAIN supplies, the

source (output) side of the external MOSFET will reach the

drain (input) voltage in a time given by:

DELAY

GATE

DRAIN

GATE SOURCE

(

)

()

Table 1 provides a reference list of the expected GATE

output slew rate for the 3.3V and 5V supplies using several

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